512Mb: x4, x8, x16 DDR2 SDRAM
Features
DDR2 SDRAM
MT47H128M4 – 32 Meg x 4 x 4 Banks
MT47H64M8 – 16 Meg x 8 x 4 Banks
MT47H32M16 – 8 Meg x 16 x 4 Banks
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Options
RoHS compliant
VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
4 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1 tCK
Selectable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8,192-cycle refresh
On-die termination (ODT)
Industrial temperature (IT) option
Automotive temperature (AT) option
Supports JEDEC clock jitter specification
Notes:
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
512Mb_DDR2_x4x8x16_D1.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Marking
• Configuration
– 128 Meg x 4 (32 Meg x 4 x 4 banks)
128M4
– 64 Meg x 8 (16 Meg x 8 x 4 banks)
64M8
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
32M16
• FBGA package (Pb-free)
– 84-ball FBGA (12mm x 12.5mm) Rev. B
CC
– 84-ball FBGA (10mm x 12.5mm) Rev. D
BN
– 84-ball FBGA (8mm x 12.5mm) Rev. F
HR
– 60-ball FBGA (12mm x 10mm) Rev. B
CB
– 60-ball FBGA (10mm x 10mm) Rev. D
B6
– 60-ball FBGA (8mm x 10mm) Rev. F
CF
• FBGA package (with lead)
– 84-ball FBGA (12mm x 12.5mm) Rev. B
GC
– 84-ball FBGA (10mm x 12.5mm) Rev. D
FN
– 84-ball FBGA (8mm x 12.5mm) Rev. F
HW
– 60-ball FBGA (12mm x 10mm) Rev. B
GB
– 60-ball FBGA (10mm x 10mm) Rev. D
F6
– 60-ball FBGA (8mm x 10mm) Rev. F
JN
• Timing – cycle time
– 2.5ns @ CL = 5 (DDR2-800)
-25E
– 2.5ns @ CL = 6 (DDR2-800)
-25
– 3.0ns @ CL = 4 (DDR2-667)
-3E
– 3.0ns @ CL = 5 (DDR2-667)
-3
– 3.75ns @ CL = 4 (DDR2-533)
-37E1
– 5.0ns @ CL = 3 (DDR2-400)
-5E1
• Self refresh
– Standard
None
– Low-power
L
• Operating temperature
– Commercial (0°C ≤ TC ≤ 85°C)
None
– Industrial (–40°C ≤ TC ≤ 95°C;
IT
–40°C ≤ TA ≤ 85°C)
– Automotive, Revision :D only
AT
(–40°C ≤ TC, TA≤ 105°C)
• Revision
:B1/:D1/:F
1
1. Not recommended for new designs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512Mb: x4, x8, x16 DDR2 SDRAM
Features
Table 1:
Key Timing Parameters
Data Rate (MT/s)
Speed Grade
CL = 3
CL = 4
CL = 5
CL = 6
CL = 7
-25E
-25
-3E
-3
-37E
-5E
400
400
400
400
400
400
533
533
667
533
533
400
800
667
667
667
–
–
800
800
–
–
–
–
–
–
–
–
–
–
Table 2:
RC (ns)
55
55
54
55
55
55
Addressing
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
Figure 1:
t
128 Meg x 4
64 Meg x 8
32 Meg x 16
32 Meg x 4 x 4 banks
8K
A0–A13 (16K)
BA0–BA1 (4)
A0–A9, A11 (2K)
16 Meg x 8 x 4 banks
8K
A0–A13 (16K)
BA0–BA1 (4)
A0–A9 (1K)
8 Meg x 16 x 4 banks
8K
A0–A12 (8K)
BA0–BA1 (4)
A0–A9 (1K)
512Mb DDR2 Part Numbers
Example Part Number: MT47H64M8HR-3:F
Package
Configuration
Speed
Revision
{
MT47H
:
Configuration
:B/:D/:F Revision
128 Meg x 4
128M4
64 Meg x 8
64M8
32 Meg x 16
32M16
Package
Notes:
Options
Pb-Free With Lead
L
Low-Power
IT
Industrial
AT
Automotive
84-ball 12mm x 12.5mm FBGA
CC
84-ball 10mm x 12.5mm FBGA
BN
FN
84-ball 8mm x 12.5mm FBGA
HR
HW
-5E
Speed Grade
tCK = 5ns, CL = 3
60-ball 12mm x 10mm FBGA
CB
GB
-37E
tCK = 3.75ns, CL = 4
60-ball 10mm x 10mm FBGA
B6
F6
-3
tCK = 3ns, CL = 5
60-ball 8mm x 10mm FBGA
CF
JN
-3E
tCK = 3ns, CL = 4
-25
tCK = 2.5ns, CL = 6
-25E
tCK = 2.5ns, CL = 5
GC
1. Not all speeds and configurations are available in all packages.
FBGA Part Number System
Due to space limitations, FBGA-packaged components have an abbreviated part
marking that is different from the part number. For a quick conversion of an FBGA code,
see the FBGA Part Marking Decoder on Micron’s Web site: www.micron.com.
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
512Mb_DDR2_x4x8x16_D1.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Industrial Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Automotive Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Electrical Specifications – Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Electrical Specifications – IDD Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
IDD7 Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
AC Timing Operating Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
AC and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
ODT DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Input Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Output Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Power and Ground Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
AC Overshoot/Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Input Slew Rate Derating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
LOAD MODE (LM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
ACTIVATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Mode Register (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Extended Mode Register (EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Extended Mode Register 2 (EMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Extended Mode Register 3 (EMR 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
ACTIVATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Precharge Power-Down Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ODT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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512Mb_DDR2_x4x8x16_TOC.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Table of Contents
MRS Command to ODT Update Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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512Mb_DDR2_x4x8x16_TOC.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
State Diagram
State Diagram
Figure 2:
Simplified State Diagram
CKE L
Initialization
sequence
OCD
default
Self
refreshing
SR
PRE
Setting
MRS
EMRS
H
CKE
Idle
all banks
precharged
(E)MRS
REFRESH
CK
E
H
CK
E
E
Refreshing
L
CK
L
Precharge
powerdown
ACT
CKE L
Automatic Sequence
Command Sequence
CKE L
ACT = ACTIVATE
CKE H = CKE HIGH, exit power-down or self refresh
CKE L = CKE LOW, enter power-down
(E)MRS = (Extended) mode register set
PRE = PRECHARGE
PRE A = PRECHARGE ALL
READ = READ
READ AP = READ with auto precharge
REFRESH = REFRESH
SR = SELF REFRESH
WRITE = WRITE
WRITE AP = WRITE with auto precharge
Activating
CKE
Active
powerdown
L
CK
E
CK H
EL
Bank
active
RE
E
RIT
AD
W
WRITE
READ
WRITE
Reading
REA
P
DA
P
AP
W
RIT
AD
RE
EA
P
Writing
EA
IT
WR
READ AP
Writing
with
auto
precharge
PR
EA
E,
PR
PR
E
E,
A
PR
WRITE AP
READ
Reading
with
auto
precharge
PRE, PRE A
Precharging
Notes:
1. This diagram provides the basic command flow. It is not comprehensive and does not identify all timing requirements or possible command restrictions such as multibank interaction,
power down, entry/exit, etc.
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core1.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Functional Description
Functional Description
The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or
write access for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, one-clockcycle data transfer at the internal DRAM core and four corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O balls.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
during READs and by the memory controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs. The x16 offering has two data
strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS,
UDQS#).
The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK
going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS as well as to both edges of CK.
Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVATE command are used to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR2 SDRAM provides for programmable READ or WRITE burst lengths of four or
eight locations. DDR2 SDRAM supports interrupting a burst READ of eight with another
READ or a burst WRITE of eight with another WRITE. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst access.
As with standard DDR SDRAMs, the pipelined, multibank architecture of DDR2 SDRAMs
allows for concurrent operation, thereby providing high, effective bandwidth by hiding
row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength
outputs are SSTL_18-compatible.
Industrial Temperature
The industrial temperature (IT) option, if offered, has two simultaneous requirements:
ambient temperature surrounding the device cannot be less than –40°C or greater than
+85°C, and the case temperature cannot be less than –40°C or greater than +95°C. JEDEC
specifications require the refresh rate to double when TC exceeds +85°C; this also
requires use of the high-temperature self refresh option. Additionally, ODT resistance
and the input/output impedance must be derated when TC is < 0°C or > +85°C.
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DDR2_x4x8x16_Core1.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Functional Description
Automotive Temperature
The automotive temperature (AT) option, if offered, has two simultaneous requirements: ambient temperature surrounding the device cannot be less than –40°C or
greater than +105°C, and the case temperature cannot be less than –40°C or greater than
+105°C. JEDEC specifications require the refresh rate to double when TC exceeds +85°C;
this also requires use of the high-temperature self refresh option. Additionally, ODT
resistance and the input/output impedance must be derated when TC is < 0°C or >
+85°C.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL-enabled mode of operation.
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated
otherwise. Additionally, the x16 is divided into 2 bytes: the lower byte and the upper
byte. For the lower byte (DQ0–DQ7), DM refers to LDM and DQS refers to LDQS. For
the upper byte (DQ8–DQ15), DM refers to UDM and DQS refers to UDQS.
• Complete functionality is described throughout the document, and any page or
diagram may have been simplified to convey a topic and may not be inclusive of all
requirements.
• Any specific requirement takes precedence over a general statement.
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DDR2_x4x8x16_Core1.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Functional Block Diagrams
Functional Block Diagrams
The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory. It is internally configured as a multi-bank DRAM.
Figure 3:
128 Meg x 4 Functional Block Diagram
ODT
CS#
RAS#
CAS#
WE#
Control
logic
Command
decode
CKE
CK
CK#
Mode
registers
16
Refresh 14
Row- 14
counter
address
MUX
14
Bank 3
Bank 3
Bank 2
Bank 2
Bank 1
Bank 1
Bank 0
Bank 0
rowmemory
address 16,384
array
latch and
(16,384 x 512 x 16)
decoder
Column 0, Column 1
4
4
16 READ
4
latch
4
A0–A13,
BA0, BA1
Address
16 register
2
512
(x16)
Column
decoder
11
Columnaddress
counter/
latch
9
2
Data
DRVRS
Input
registers
1
1
1
1
16
Bank
control
logic
4
sw1
sw2 sw3
R1
R2
R3
R1
R2
R3
DQ0–DQ3
DQS
generator DQS, DQS#
8,192
I/O gating
DM mask logic
DLL
MUX
ODT control VDDQ
sw1 sw2 sw3
2
Sense amplifiers
2
CK, CK#
sw1
sw2 sw3
R1
R2
R3
R1
R2
R3
4
WRITE
FIFO Mask 1
and
1
16
drivers
4
internal
CK out
CK, CK#
16 4
CK in
Data 4
4
R1
R2
R3
4
4
R1
R2
R3
1
1
1
4
4
DQS, DQS#
RCVRS
sw1
4
sw2 sw3
DM
Column 0, Column 1
2
VssQ
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512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Functional Block Diagrams
Figure 4:
64 Meg x 8 Functional Block Diagram
ODT
Control
logic
Command
decode
CKE
CK
CK#
CS#
RAS#
CAS#
WE#
Mode
registers
16
Refresh
counter 14
14
Row- 14
address
MUX
Bank 3
Bank 3
Bank 2
Bank 2
Bank 1
Bank 1
Bank 0
Bank 0
rowMemory
address 16,384
latch and
array
decoder
(16,384 x 256 x 32)
Column 0, Column 1
32
8
8
8
READ
latch
A0–A13,
BA0, BA1
16
Address
register
I/O gating
DM mask logic
Bank
control
logic
2
10
2
32
internal
CK, CK#
2
sw1
sw2
sw3
R1
R2
R3
R1
R2
R3
sw1
sw2
sw3
R1
R2
R3
DQS, DQS#
R1
R2
R3
RDQS#
4
WRITE
FIFO Mask 1
1
and
drivers
8
CK out
32 8
CK in
Data 8
sw1
sw2
sw3
8
R1
R2
R3
8
8
R1
R2
R3
1
1
1
RCVRS
8
8
8
RDQS
DM
Column 0, Column 1
VssQ
2
Figure 5:
DQ0–DQ7
DQS, DQS#
Input
registers
1
1
1
1
32
Column
decoder
8
DRVRS
Data
DQS
generator
256
(x32)
Columnaddress
counter/
latch
8
MUX
8,192
2
ODT control VDDQ
sw1 sw2 sw3
DLL
8
Sense amplifiers
CK, CK#
32 Meg x 16 Functional Block Diagram
ODT
CS#
RAS#
CAS#
WE#
Control
logic
Command
decode
CKE
CK
CK#
Column 0, Column 1
Mode
registers
Refresh
counter 13
15
13
Rowaddress
MUX
Bank 3
Bank 3
Bank 2
Bank 2
Bank 1
Bank 1
Bank 0
Bank 0
13
rowaddress 8,192
Memory
latch and
array
decoder
(8,192 x 256 x 64)
Sense amplifiers
64
READ
latch
MUX
16
16
A0–A12,
BA0, BA1
15 Address
register
2
10
I/O gating
DM mask
logic
Bank
control
logic
Columnaddress
counter/
latch
Input
registers
2
64
WRITE
FIFO
64 and
drivers
256
(x64)
8
Column
decoder
16
Internal
CK, CK#
CK out
CK in
2
Column 0, Column 1
DRVRS
Data
DQS
generator
16,384
2
CK, CK#
ODT control VDDQ
sw1 sw2 sw3
DLL
16
16
sw1
sw2
sw3
R1
R2
R3
R1
R2
R3
sw1
sw2
sw3
R1
R2
R3
R1
R2
R3
4
UDQS, UDQS#
LDQS, LDQS#
2
2
2
8
2
2
Mask
2
2
16
16
16
sw1
sw2
sw3
16
16
16
R1
R2
R3
16
R1
R2
R3
64
Data
DQ0–DQ15
16
2
UDQS, UDQS#
LDQS, LDQS#
RCVRS
16
UDM, LDM
4
VssQ
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512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 6:
60-Ball FBGA – x4, x8 Ball Assignments (Top View)
1
2
3
VDD
NF, RDQS#/NU
VSS
4
5
6
7
8
9
A
VSSQ DQS#/NU VDDQ
B
NF, DQ6
VSSQ
DM, DM/RDQS
DQS
VSSQ
NF, DQ7
VDDQ
DQ1
VDDQ
VDDQ
DQ0
VDDQ
NF, DQ4
VSSQ
DQ3
DQ2
VSSQ
NF, DQ5
VDDL
VREF
VSS
VSSDL
CK
VDD
CKE
WE#
RAS#
CK#
ODT
BA0
BA1
CAS#
CS#
A10
A1
A2
A0
A3
A5
A6
A4
A7
A9
A11
A8
A12
RFU
RFU
A13
C
D
E
F
G
RFU
H
VDD
J
VSS
K
VSS
L
VDD
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512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
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©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignments and Descriptions
Figure 7:
84-Ball FBGA – x16 Ball Assignments (Top View)
1
2
3
4
5
6
7
8
9
VDD
NC
VSS
DQ14
VSSQ
UDM
UDQS
VSSQ
DQ15
VDDQ
DQ9
VDDQ
VDDQ
DQ8
VDDQ
DQ12
VSSQ
DQ11
DQ10
VSSQ
DQ13
VDD
NC
VSS
DQ6
VSSQ
LDM
LDQS
VSSQ
DQ7
VDDQ
DQ1
VDDQ
VDDQ
DQ0
VDDQ
DQ4
VSSQ
DQ3
DQ2
VSSQ
DQ5
VDDL
VREF
VSS
VSSDL
CK
VDD
CKE
WE#
RAS#
CK#
ODT
BA0
BA1
CAS#
CS#
A10
A1
A2
A0
A3
A5
A6
A4
A7
A9
A11
A8
A12
RFU
RFU
RFU
A
VSSQ UDQS#/NU VDDQ
B
C
D
E
VSSQ LDQS#/NU VDDQ
F
G
H
J
K
L
RFU
M
VDD
N
VSS
P
VSS
R
VDD
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512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignments and Descriptions
Table 3:
FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions
x16 Ball
Number
x4, x8 Ball
Number
Symbol
Type
Description
M8, M3, M7,
N2, N8, N3,
N7, P2, P8,
P3, M2,
P7, R2
–
A0, A1, A2,
A3, A4, A5,
A6, A7, A8,
A9, A10,
A11, A12
Input
–
H8, H3, H7,
J2, J8, J3,
J7, K2, K8,
K3, H2,
K7, L2,
L8
A0, A1, A2,
A3, A4, A5,
A6, A7, A8,
A9, A10,
A11, A12,
A13
Input
L2, L3
G2, G3,
BA0, BA1
Input
J8, K8
E8, F8
CK, CK#
Input
K2
F2
CKE
Input
L8
G8
CS#
Input
Address inputs: Provide the row address for ACTIVATE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of
the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one bank (A10 LOW, bank selected by BA0–BA2) or all
banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command.
Address inputs: Provide the row address for ACTIVATE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of
the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one bank (A10 LOW, bank selected by BA0–BA2) or all
banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command.
Bank address inputs: BA0–BA1 define the bank to which an
ACTIVATE, READ, WRITE, or PRECHARGE command is being
applied. BA0–BA1 define which mode register including MR,
EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE
command.
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and the negative edge of CK#. Output data (DQ and
DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and disables
(registered LOW) clocking circuitry on the DDR2 SDRAM. The
specific circuitry that is enabled/disabled is dependent on the
DDR2 SDRAM configuration and operating mode. CKE LOW
provides PRECHARGE power-down and SELF REFRESH
operations (all banks idle), or active power-down (row active in
any bank). CKE is synchronous for power-down entry, powerdown exit, OUTPUT DISABLE, and for self refresh entry. CKE is
asynchronous for SELF REFRESH exit. Input buffers (excluding
CK, CK#, CKE, and ODT) are disabled during power-down. Input
buffers (excluding CKE) are disabled during SELF REFRESH. CKE
is an SSTL_18 input but will detect a LVCMOS LOW level once
VDD is applied during first power-up. After VREF has become
stable during the power-on and initialization sequence, it must
be maintained for proper operation of the CKE receiver. For
proper SELF-REFRESH operation, VREF must be maintained.
Chip select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS# is registered HIGH. CS# provides for external
rank selection on systems with multiple ranks. CS# is considered
part of the command code.
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512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
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512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignments and Descriptions
Table 3:
FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions (continued)
x16 Ball
Number
x4, x8 Ball
Number
Symbol
Type
Description
F3, B3
B3
LDM, UDM
DM
Input
K9
F9
ODT
Input
K7, L7,
K3
G8, G2, H7,
H3, H1, H9,
F1, F9, C8,
C2, D7, D3,
D1, D9, B1,
B9
–
F7, G7,
F3
–
RAS#, CAS#,
WE#
DQ0–DQ2,
DQ3–DQ5,
DQ6–DQ8,
DQ9–DQ11,
DQ12–DQ14,
DQ15
DQ0–DQ2,
DQ3–DQ5,
DQ6–DQ7
DQ0–DQ2,
DQ3
DQS, DQS#
Input
I/O
Input data mask: DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with the
input data during a WRITE access. DM is sampled on both edges
of DQS. Although the DM balls are input-only, the DM loading is
designed to match that of the DQ and DQS balls. LDM is DM for
lower byte DQ0–DQ7 and UDM is DM for upper byte
DQ8–DQ15.
On-die termination: ODT enables (registered HIGH) and
disables (resgistered LOW) termination resistance internal to the
DDR2 SDRAM. When enabled, ODT is only applied to each of
the following balls: DQ0–DQ15, LDM, UDM, LDQS, LDQS#,
UDQS, and UDQS# for the x16; DQ0–DQ7, DQS, DQS#, RDQS,
RDQS#, and DM for the x8; DQ0–DQ3, DQS, DQS#, and DM for
the x4. The ODT input will be ignored if disabled via the LOAD
MODE command.
Command inputs: RAS#, CAS#, and WE# (along with CS#)
define the command being entered.
Data input/output: Bidirectional data bus for 32 Meg x 16.
I/O
Data input/output: Bidirectional data bus for 64 Meg x 8.
I/O
Data input/output: Bidirectional data bus for 128 Meg x 4.
–
C8, C2, D7,
D3, D1, D9,
B1, B9
C8, C2, D7,
D3
B7, A8
F7, E8
–
B7, A8
–
–
B3, A2
–
I/O
Data strobe: Output with read data, input with write data for
source synchronous operation. Edge-aligned with read data,
center-aligned with write data. DQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.
LDQS, LDQS#
I/O
Data strobe for lower byte: Output with read data, input
with write data for source synchronous operation. Edge-aligned
with read data, center-aligned with write data. LDQS# is only
used when differential data strobe mode is enabled via the
LOAD MODE command.
UDQS, UDQS#
I/O
Data strobe for upper byte: Output with read data, input
with write data for source synchronous operation. Edge-aligned
with read data, center-aligned with write data. UDQS# is only
used when differential data strobe mode is enabled via the
LOAD MODE command.
RDQS, RDQS# Output Redundant data strobe: For 64 Meg x 8 only. RDQS is enabled/
disabled via the load mode command to the extended mode
register (EMR). When RDQS is enabled, RDQS is output with
read data only and is ignored during write data. When RDQS is
disabled, ball B3 becomes data mask (see DM ball). RDQS# is
only used when RDQS is enabled and differential data strobe
mode is enabled.
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512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignments and Descriptions
Table 3:
FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions (continued)
x16 Ball
Number
x4, x8 Ball
Number
Symbol
A1, E1, M9,
R1, J9
A9, C1, C3,
C7, C9, G3, E9,
G1, G7, G9
J1
J2
A3, E3, J3, N1,
P9
J7
A7, B2, B8,
D2, D8, E7, F2,
F8, H2, H8
A2, E2
–
A1, E9, L1, H9
VDD
A9, C1, C3, C7,
C9
VDDQ
Supply DQ power supply: 1.8V ±0.1V. Isolated on the device for
improved noise immunity.
E1
E2
A3, E3, J1, K9
VDDL
VREF
VSS
Supply DLL power supply: 1.8V ±0.1V.
Supply SSTL_18 reference voltage (VDDQ/2).
Supply Ground.
E7
A7, B2, B8, D2,
D8
VSSDL
VSSQ
Supply DLL ground: Isolated on the device from VSS and VSSQ.
Supply DQ ground: Isolated on the device for improved noise
immunity.
–
B1, B9, D1, D9
NC
NF
–
–
A8, E8
A2, A8
NU
–
L1, R8, R3, R7
G1, L3, L7
RFU
–
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512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Type
Description
Supply Power supply: 1.8V ±0.1V.
No connect: These balls should be left unconnected.
No function: x8: these balls are used as DQ4–DQ7; x4: they are
no function.
Not used: If EMR(E10) = 0: x16, A8 = UDQS# and E8 = LDQS#;
x8, A2 = RDQS# and A8 = DQS#; x4, A2 = NU and A8 = NU. If
EMR(E10) = 1: x16, A8 = NU and E8 = NU; x8, A2 = NU and
A8 = NU; x4, A2 = NU and A8 = NU.
Reserved for future use: Bank address BA2. Row address bits
A13 (x16 only), A14, and A15.
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Package Dimensions
Package Dimensions
Figure 8:
60-Ball FBGA (12mm x 10mm) – x4, x8
0.8 ±0.1
SEATING
PLANE
0.12 C
C
60X Ø0.45
SOLDER BALL
DIAMETER REFERS
TO POST-REFLOW
CONDITION.
6.4
0.8
TYP
BALL A1 ID
CL
8.0
0.25 MIN
BALL A1 ID Location
10.0 ±0.15
0.8 TYP
CL
12.0 ±0.15
Notes:
1.20 MAX
1. All dimensions are in millimeters.
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512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Package Dimensions
Figure 9:
60-Ball FBGA (10mm x 10mm) – x4, x8
0.8 ±0.1
SEATING PLANE
C
0.12 C
6.4
60X Ø0.45
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION.
0.80 TYP
BALL A1 ID
0.25 MIN
BALL A1 ID Location
8.0
CL
10.0 ±0.15
0.8 TYP
CL
10.0 ±0.15
Notes:
1.20 MAX
1. All dimensions are in millimeters.
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512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Package Dimensions
Figure 10:
60-Ball FBGA (8mm x 10mm) – x4, x8
0.8 ±0.1
SEATING PLANE
C
0.12 C
60X Ø0.45
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION.
6.40
0.80 TYP
BALL A1 ID
CL
8.0
0.25 MIN
BALL A1 ID Location
10.0 ±0.15
0.80 TYP
CL
8.0 ±0.15
Notes:
1.20 MAX
1. All dimensions are in millimeters.
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512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Package Dimensions
Figure 11:
84-Ball FBGA (12mm x 12.5mm) – x16
0.8 ±0.1
SEATING
PLANE
0.12 C
C
84X Ø0.45
SOLDER BALL
DIAMETER REFERS
TO POST-REFLOW
CONDITION.
6.4
0.8
TYP
BALL A1 ID
0.25 MIN
CL
11.2
BALL A1 ID Location
12.5 ±0.15
0.80 TYP
CL
12.0 ±0.15
Notes:
1.2 MAX
1. All dimensions are in millimeters.
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Package Dimensions
Figure 12:
84-Ball FBGA (10mm x 12.5mm) – x16
0.8 ±0.1
SEATING PLANE
C
0.12 C
6.4
84X ∅0.45
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION.
0.8
TYP
0.25 MIN
BALL A1 ID
BALL A1 ID Location
12.5 ±0.15
CL
11.2
0.8 TYP
CL
10.0 ±0.15
1.20 MAX
Notes:
1. All dimensions are in millimeters.
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512Mb: x4, x8, x16 DDR2 SDRAM
Package Dimensions
Figure 13:
84-Ball FBGA (8mm x 12.5mm) – x16
0.8 ±0.1
SEATING PLANE
A
0.12 A
84X ∅ 0.45
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION.
6.4
0.80 TYP
0.25 MIN
BALL A1 ID
BALL A1 ID Location
0.80 TYP
12.5 ±0.15
CL
11.2
CL
8.0 ±0.15
Notes:
1.20 MAX
1. All dimensions are in millimeters.
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FBGA Package Capacitance
FBGA Package Capacitance
Table 4:
Input Capacitance
Parameter
Input capacitance: CK, CK#
Delta input capacitance: CK, CK#
Input capacitance: Address balls, bank address balls,
CS#, RAS#, CAS#, WE#, CKE, ODT
Delta input capacitance: Address balls, bank address
balls, CS#, RAS#, CAS#, WE#, CKE, ODT
Input/output capacitance: DQ, DQS, DM, NF
Delta input/output capacitance: DQ, DQS, DM, NF
Notes:
Symbol
Min
Max
Units
Notes
CCK
CDCK
CI
1.0
–
1.0
2.0
0.25
2.0
pF
pF
pF
1
2, 3
1, 4
CDI
–
0.25
pF
2, 3
CIO
CDIO
2.5
–
4.0
0.5
pF
pF
1, 5
3, 6
1. This parameter is sampled. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VREF = VSS, f = 100 MHz,
TC = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak-to-peak) = 0.1V. DM input is grouped with I/O
balls, reflecting the fact that they are matched in loading.
2. The input capacitance per ball group will not differ by more than this maximum amount for
any given device.
3. ΔC are not pass/fail parameters but rather targets.
4. Reduce MAX limit by 0.25pF for -25, -25E speed devices.
5. Reduce MAX limit by 0.5pF for -3, -3E, -25, -25E speed devices.
6. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum
amount for any given device.
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Electrical Specifications – Absolute Ratings
Electrical Specifications – Absolute Ratings
Stresses greater than those listed in Table 5 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions oustide those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
adversely affect reliability.
Table 5:
Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
Notes
VDD supply voltage relative to VSS
VDDQ supply voltage relative to VSSQ
VDDL supply voltage relative to VSSL
Voltage on any ball relative to VSS
Input leakage current; Any input 0V ≤ VIN ≤ VDD; All other balls
not under test = 0V
Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ and ODT
disabled
VREF leakage current; VREF = Valid VREF level
VDD
VDDQ
VDDL
VIN, VOUT
II
–1.0
–0.5
–0.5
–0.5
–5
+2.3
+2.3
+2.3
+2.3
+5
V
V
V
V
µA
1
1, 2
1
3
IOZ
–5
+5
µA
IVREF
–2
+2
µA
Notes:
1. VDD, VDDQ, and VDDL must be within 300mV of each other at all times.
2. VREF ≤ 0.6 × VDDQ; however, VREF may be ≥ VDDQ provided that VREF ≤ 300mV.
3. Voltage on any I/O may not exceed voltage on VDDQ.
Temperature and Thermal Impedance
It is imperative that the DDR2 SDRAM device’s temperature specifications, shown in
Table 6 on page 23, be maintained in order to ensure the junction temperature is in the
proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’s thermal impedances
correctly. The thermal impedances are listed in Table 7 on page 24 for the applicable and
available die revision and packages.
Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08, “Thermal Applications,” prior to using the thermal impedances
listed in Table 7 on page 24. For designs that are expected to last several years and
require the flexibility to use several DRAM die shrinks, consider using final target theta
values (rather than existing values) to account for increased thermal impedances from
the die size reduction.
The DDR2 SDRAM device’s safe junction temperature range can be maintained when
the TC specification is not exceeded. In applications where the device’s ambient temperature is too high, use of forced air and/or heat sinks may be required in order to satisfy
the case temperature specifications.
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Electrical Specifications – Absolute Ratings
Table 6:
Temperature Limits
Parameter
Symbol
Min
Max
Units
Notes
TSTG
TC
TC
TA
TC
TA
–55
0
–40
–40
–40
–40
+150
+85
+95
+85
+105
+105
°C
°C
°C
°C
°C
°C
1
2, 3
2, 3, 4
4, 5
2, 3, 4
4, 5
Storage temperature
Operating temperature: commercial
Operating temperature: industrial
Operating temperature: automotive
Notes:
Figure 14:
1. MAX storage case temperature; TSTG is measured in the center of the package, as shown in
Figure 14. This case temperature limit is allowed to be exceeded briefly during package
reflow, as noted in Micron technical note TN-00-15, “Recommended Soldering Parameters.”
2. MAX operating case temperature; TC is measured in the center of the package, as shown in
Figure 14.
3. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
4. Both temperature specifications must be satisfied.
5. Operating ambient temperature surrounding the package.
Example Temperature Test Point Location
Test point
Length (L)
0.5 (L)
0.5 (W)
Width (W)
Lmm x Wmm FGBA
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Electrical Specifications – Absolute Ratings
Table 7:
Die
Revision
B
Thermal Impedance
Package
θ JA (°C/W)
θ JA (°C/W)
θ JA (°C/W)
Substrate Airflow = 0m/s Airflow = 1m/s Airflow = 2m/s θ JB (°C/W) θ JC (°C/W) Notes
60-ball
84-ball
D
60-ball
84-ball
F
60-ball
84-ball
Last shrink
target
60-ball
84-ball
Notes:
2-layer
4-layer
2-layer
4-layer
2-layer
4-layer
2-layer
4-layer
2-layer
4-layer
2-layer
4-layer
2-layer
4-layer
2-layer
4-layer
53.2
37.4
50.2
34.9
56.9
40.6
56.8
40.3
71.4
53.6
65.8
50
72
54
66
50
40.0
30.9
36.8
28.0
43.6
34.1
42.8
33.2
54.1
44.5
50.4
41.3
55
45
52
42
37.2
27.7
32.1
25.5
38.5
31.3
37.7
30.4
47.5
40.5
44.3
37.7
48
41
45
39
27.5
24.2
24.5
21.3
30.6
27.0
24.8
23.5
33.7
33.5
30.7
30.5
34
34
32
32
2.9
1
3.1
3.8
1
3.9
5.5
1
4.1
5.5
2
4.5
1. Thermal resistance data is based on a number of samples from multiple lots and should be
viewed as a typical number.
2. This is an estimate; simulated number and actual results could vary.
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Electrical Specifications – IDD Parameters
Electrical Specifications – IDD Parameters
IDD Specifications and Conditions
Table 8:
General IDD Parameters
IDD Parameters
-187E
CL (IDD)
t
RCD (IDD)
t
RC (IDD)
tRRD (IDD) - x4/x8 (1KB)
t
RRD (IDD) - x16 (2KB)
tCK (IDD)
t
RAS MIN (IDD)
tRAS MAX (IDD)
tRP (IDD)
tRFC (IDD)
tFAW (IDD) - x4/x8
tFAW (IDD) - x16
7
13.125
58125
7.5
10
1.875
45
70,000
13.125
105
-25E
-25
-3E
-3
-37E
5
6
4
5
4
12.5
15
12
15
15
57.5
60
57
60
60
7.5
7.5
7.5
7.5
7.5
10
10
10
10
10
2.5
2.5
3
3
3.75
45
45
45
45
45
70,000
70,000
70,000
70,000
70,000
12.5
15
12
15
15
105
105
105
105
105
Pattern determined by Table 9 on page 25
Pattern determined by Table 9 on page 25
-5E
3
15
55
7.5
10
5
40
70,000
15
105
Units
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IDD7 Conditions
Detailed IDD7 timings are shown below. Where general IDD parameters in Table 8 on
page 25 conflict with pattern requirements of Table 9, then Table 9 requirements take
precedence.
Table 9:
IDD7 Timing Patterns (4-Bank Interleave READ Operation)
Speed Grade
IDD7 Timing Patterns
Timing patterns for 4-bank x4/x8/x16 devices
-187E
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D
-25E
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
-25
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D
-3E
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
-3
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
-37E
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-5E
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
Notes:
1. A = ACTIVATE; RA = READ with auto precharge; D = DESELECT.
2. All banks are being interleaved at tRC (IDD) without violating tRRD (IDD) using a BL = 4.
3. Control and address bus inputs are stable during DESELECTs.
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Electrical Specifications – IDD Parameters
Table 10:
DDR2 IDD Specifications and Conditions
Notes: 1–7 (page 27) apply to the entire table
Parameter/Condition
Operating one bank active-precharge current:
t
CK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are
switching
Operating one bank active-read-precharge
current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK
= tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD),
t
RCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are switching;
Data pattern is same as IDD4W
Precharge power-down current: All banks idle; tCK
= tCK (IDD); CKE is LOW; Other control and address
bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other
control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other
control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All banks open;
tCK = tCK (IDD); CKE is LOW; Other control and
address bus inputs are stable; Data bus inputs are
floating
Active standby current: All banks open;
(IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Other control and address bus inputs are switching;
Data bus inputs are switching
Operating burst write current: All banks open,
continuous burst writes; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are
switching
Operating burst read current: All banks open,
continuous burst reads, IOUT = 0mA; BL = 4,
CL = CL (IDD), AL = 0; tCK = tCK (IDD),
t
RAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
Burst refresh current: tCK = tCK (IDD); refresh
command at every tRFC (IDD) interval; CKE is HIGH,
CS# is HIGH between valid commands; Other control
and address bus inputs are switching; Data bus inputs
are switching
Symbol Configuration
-3E/-3
-37E
-5E
Units
IDD0
x4, x8
x16
100
135
90
120
80
110
80
110
mA
IDD1
x4, x8
x16
115
165
105
150
95
135
90
130
mA
IDD2P
x4, x8, x16
7
7
7
7
mA
IDD2Q
x4, x8
x16
50
65
45
55
40
45
35
40
mA
IDD2N
x4, x8
x16
55
70
50
60
45
50
40
45
mA
IDD3P
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
x4, x8
x16
40
35
30
25
mA
12
12
12
12
70
75
65
70
55
60
45
50
mA
IDD4W
x4, x8
x16
195
295
170
250
140
205
115
160
mA
IDD4R
x4, x8
x16
205
275
180
235
145
195
115
155
mA
IDD5
x4, x8
x16
230
230
180
185
170
175
165
170
mA
IDD3N
tCK= tCK
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512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
-25E/
-25
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512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters
Table 10:
DDR2 IDD Specifications and Conditions (continued)
Notes: 1–7 (page 27) apply to the entire table
Parameter/Condition
Symbol Configuration
Self refresh current: CK and CK# at 0V;
CKE ≤ 0.2V; Other control and address bus inputs are
floating; Data bus inputs are floating
Operating bank interleave read current: All bank
interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD),
AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC =
t
RC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, CS# is HIGH between valid commands; Address
bus inputs are stable during deselects; Data bus
inputs are switching; See “IDD7 Conditions” on
page 25 for details
Notes:
-25E/
-25
-3E/-3
-37E
-5E
Units
IDD6
IDD6L
x4, x8, x16
7
3
7
3
7
3
7
3
mA
IDD7
x4, x8
x16
300
370
240
350
225
340
220
340
mA
1. IDD specifications are tested after the device is properly initialized. 0°C ≤ TC ≤ +85°C.
VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/2.
2. Input slew rate is specified by AC parametric test conditions (Table 8 on page 25).
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and UDQS#.
IDD values must be met with all combinations of EMR bits 10 and 11.
5. Definitions for IDD conditions:
VIN ≤ VIL(AC) MAX
VIN ≥ VIH(AC) MIN
Inputs stable at a HIGH or LOW level
Inputs at VREF = VDDQ/2
Inputs changing between HIGH and LOW every other clock cycle (once per
two clocks) for address and control signals
Switching
Inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals, not including masks or strobes
6. IDD1, IDD4R, and IDD7 require A12 in EMR1 to be enabled during testing.
7. The following IDDs must be derated (IDD limits increase) on IT-option or on AT-option
devices when operated outside of the range 0°C ≤ TC ≤ 85°C:
LOW
HIGH
Stable
Floating
Switching
TC ≤ 0°C
TC ≥ 85°C
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IDD2P and IDD3P (slow) must be derated by 4 percent; IDD4R and IDD5W must be
derated by 2 percent; and IDD6 and IDD7 must be derated by 7 percent
IDD0, IDD1, IDD2N, IDD2Q, IDD3N, IDD3P (fast), IDD4R, IDD4W, and IDD5W must be
derated by 2 percent; IDD2P must be derated by 20 percent; IDD3Pslow must be
derated by 30 percent; and IDD6 must be derated by 80 percent (IDD6 will
increase by this amount if TC < 85°C and the 2X refresh option is still enabled)
27
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AC Timing Operating Specifications
Table 11:
AC Operating Specifications and Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet 1 of 7)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported;
Notes: 1–5 (page 35) apply to the entire table; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Parameter
Clock cycle CL = 7
time
CL = 6
CL = 5
CL = 4
Clock
CL = 3
CK high-level
width
CK low-level width
28
Half clock period
Absolute CK highlevel width
Absolute CK lowlevel width
-25E
-25
-3E
-3
-37E
-5E
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
tCK
1.875
8.0
–
–
–
–
–
–
–
–
–
–
–
–
2.5
8.0
2.5
8.0
2.5
8.0
–
–
–
–
–
–
–
–
3.0
8.0
2.5
8.0
3.0
8.0
3.0
8.0
3.0
8.0
–
–
–
–
–
–
3.75
8.0
3.75
8.0
3.0
8.0
3.75
8.0
3.75
8.0
5.0
8.0
–
–
–
–
–
–
–
–
5.0
8.0
5.0
8.0
5.0
8.0
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
(AVG)
tCK
(AVG)
tCK
(AVG)
tCK
(AVG)
tCK
(AVG)
tCH
(AVG)
tCL
(AVG)
tHP
tCK
(ABS)
tCH
(ABS)
tCL
(ABS)
MIN = lesser of tCH and tCL
MAX = n/a
MIN = tCK (AVG) MIN + tJITPER (MIN)
MAX = tCK (AVG) MAX + tJITPER (MAX)
t
MIN = CK (AVG) MIN × tCH (AVG) MIN + tJITDTY (MIN)
MAX = tCK (AVG) MAX × tCH (AVG) MAX + tJITDTY (MAX)
MIN = tCK (AVG) MIN × tCL (AVG) MIN + tJITDTY (MIN)
MAX = tCK (AVG) MAX × tCL (AVG) MAX + tJITDTY (MAX)
Max Units Notes
ns
6, 7, 8,
9
0.52
tCK
10
0.52
tCK
ps
11
ps
ps
ps
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Absolute tCK
-187E
AC Operating Specifications and Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet 2 of 7)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported;
Notes: 1–5 (page 35) apply to the entire table; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Parameter
Clock Jitter
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DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Table 11:
29
Period jitter
Half period
Cycle to cycle
Cumulative error,
2 cycles
Cumulative error,
3 cycles
Cumulative error,
4 cycles
Cumulative error,
5 cycles
Cumulative error,
6–10 cycles
Cumulative error,
11–50 cycles
-187E
Symbol
Min
Max
tJITPER
–90
–75
90
75
-25E
Min
Max
-25
Min
-3E
Max
Min
-3
Max
Min
-37E
Max
Min
Max
-5E
Min
Max Units Notes
tERR
2PER
180
–132
132
–100 100
–100 100
200
–150 150
tERR
3PER
–157
157
–175
175
–175
175
–225
225
–225
225
–225
225
–225
225
ps
15
tERR
4PER
–175
175
–200
200
–200
200
–250
250
–250
250
–250
250
–250
250
ps
15
tERR
5PER
–188
188
–200
200
–200
200
–250
250
–250
250
–250
250
–250
250
ps
15, 16
tERR
6–
–250
250
–300
300
–300
300
–350
350
–350
350
–350
350
–350
350
ps
15, 16
–425
425
–450
450
–450
450
–450
450
–450
450
–450
450
–450
450
ps
15
tJITDTY
tJITCC
–100 100
–100 100
200
–150 150
–125 125
–125 125
250
–175 175
–125 125
–125 125
250
–175 175
–125 125
–125 125
250
–175 175
–125 125
–150 150
250
–175 175
ps
ps
ps
ps
12
13
14
15
10PER
tERR
11–
50PER
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
AC Operating Specifications and Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet 3 of 7)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported;
Notes: 1–5 (page 35) apply to the entire table; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Parameter
Data Strobe-Out
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DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Table 11:
30
-25E
-25
-3E
-3
-37E
-5E
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max Units Notes
DQS output access
time from CK/CK#
DQS read
preamble
DQS read
postamble
tDQSCK
–300
+300
–350
+350
–350
+350
–400
+400
–400
+400
–450
+450
–500
+500
CK/CK# to DQS
Low-Z
DQS rising edge to
CK rising edge
DQS input-high
pulse width
DQS input-low
pulse width
DQS falling to CK
rising: setup time
DQS falling from
CK rising: hold
time
Write preamble
setup time
DQS write
preamble
DQS write
postamble
WRITE command
to first DQS
transition
tLZ
1
tRPRE
tRPST
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tWPRES
tWPRE
tWPST
–
ps
19
MIN = 0.9 × tCK
MAX = 1.1 × tCK
MIN = 0.4 × tCK
MAX = 0.6 × tCK
tCK
MIN = tAC (MIN)
MAX = tAC (MAX)
MIN = –0.25 × tCK
MAX = +0.25 × tCK
MIN = 0.35 × tCK
MAX = n/a
MIN = 0.35 × tCK
MAX = n/a
MIN = 0.2 × tCK
MAX = n/a
MIN = 0.2 × tCK
MAX = n/a
ps
tCK
17,
18, 19
17,
18,
19, 20
19,
21, 22
18
tCK
18
tCK
18
tCK
18
tCK
18
ps
23, 24
tCK
18
tCK
18, 25
MIN = 0
MAX = n/a
MIN = 0.35 × tCK
MAX = n/a
MIN = 0.4 × tCK
MAX = 0.6 × tCK
MIN = WL - tDQSS
MAX = WL + tDQSS
tCK
tCK
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Data Strobe-In
-187E
AC Operating Specifications and Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet 4 of 7)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported;
Notes: 1–5 (page 35) apply to the entire table; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Parameter
Data-Out
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DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Table 11:
-25E
-25
-3E
-3
-37E
-5E
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max Units Notes
tAC
–350
+350
–400
+400
–400
+400
–450
+450
–450
+450
–500
+500
–600
+600
ps
19
tDQSQ
–
175
–
200
–
200
–
240
–
240
–
300
–
350
ps
26, 27
–
250
–
300
–
300
–
340
–
340
–
400
–
450
ps
28
ps
26,
27, 28
ps
19,
21, 29
19,
21, 22
26, 27
t
QHS
tQH
MIN = tHP - tQHS
MAX = n/a
tHZ
0
–
50
–
50
MIN = n/a
MAX = tAC (MAX)
MIN = 2 × tAC (MIN)
MAX = tAC (MAX)
MIN = tQH - tDQSQ
MAX = n/a
–
100
–
100
tDH
b
75
–
125
–
125
–
175
–
175
–
225
–
275
–
ps
tDS
a
200
–
250
–
250
–
300
–
300
–
350
–
400
–
ps
tDH
a
200
–
250
–
250
–
300
–
300
–
350
–
400
–
ps
tLZ
2
DVW
tDS
b
tDIPW
MIN = 0.35 × tCK
MAX = n/a
ps
ns
–
100
–
150
–
ps
tCK
26,
30, 31
26,
30, 31
26,
30, 31
26,
30, 31
18, 32
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Data-In
31
DQ output access
time from CK/CK#
DQS–DQ skew,
DQS to last DQ
valid, per group,
per access
DQ hold from next
DQS strobe
DQ–DQS hold, DQS
to first DQ not
valid
CK/CK# to DQ, DQS
High-Z
CK/CK# to DQ
Low-Z
Data valid output
window
DQ and DM input
setup time to DQS
DQ and DM input
hold time to DQS
DQ and DM input
setup time to DQS
DQ and DM input
hold time to DQS
DQ and DM input
pulse width
-187E
AC Operating Specifications and Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet 5 of 7)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported;
Notes: 1–5 (page 35) apply to the entire table; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Parameter
32
Input setup time
Input hold time
Input setup time
Input hold time
Input pulse width
ACTIVATE-toACTIVATE delay,
same bank
ACTIVATE-to-READ
or WRITE delay
ACTIVATE-toPRECHARGE delay
PRECHARGE period
PRECHAR 1Gb
period
ACTIVATE- x4, x8
tox16
ACTIVATE
delay
different
bank
4-bank
x4, x8
activate
x16
period
Internal READ-toPRECHARGE delay
CAS#-to-CAS#
delay
Write recovery
time
Write AP recovery
+ precharge time
Internal WRITE-toREAD delay
LOAD MODE cycle
time
-187E
-25E
-25
-3E
-3
-37E
-5E
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
tIS
b
tIH
b
tIS
a
tIH
a
t
tRC
125
200
325
325
0.6
54
–
–
–
–
–
–
175
250
375
375
0.6
55
–
–
–
–
–
–
175
250
375
375
0.6
55
–
–
–
–
–
–
200
275
400
400
0.6
54
–
–
–
–
–
–
200
275
400
400
0.6
55
–
–
–
–
–
–
250
375
500
500
0.6
55
–
–
–
–
–
–
350
475
600
600
0.6
55
–
–
–
–
–
–
ps
ps
ps
ps
t
CK
ns
31, 33
31, 33
31, 33
31, 33
18, 32
18, 34
tRCD
13.125
–
12.5
–
15
–
12
–
15
–
15
–
15
–
ns
18
tRAS
40
70K
40
70K
40
70K
40
70K
40
70K
40
70K
40
70K
ns
tRP
13.125
13.125
15
–
–
–
12.5
12.5
15
–
–
–
15
15
17.5
–
–
12
12
15
–
–
15
15
18
–
–
15
15
18.75
–
–
15
15
20
–
–
ns
ns
ns
18,
34, 35
18, 36
18, 36
18, 36
7.5
10
–
–
7.5
10
–
–
7.5
10
–
–
7.5
10
–
–
7.5
10
–
–
7.5
10
–
–
7.5
10
–
–
ns
ns
18, 37
18, 37
tFAW
35
45
–
–
35
45
–
–
35
45
–
–
37.5
50
–
–
37.5
50
–
–
37.5
50
–
–
37.5
50
–
–
ns
ns
18, 38
18, 38
tRTP
7.5
–
7.5
–
7.5
–
7.5
–
7.5
–
7.5
–
7.5
–
ns
tCCD
2
–
2
–
2
–
2
–
2
–
2
–
2
–
tCK
18,
37, 39
18
tWR
15
–
15
–
15
–
15
–
15
–
15
–
15
–
ns
18, 37
tDAL
tWR +
–
tWR +
–
tWR +
–
tWR +
–
tWR +
–
tWR +
–
tWR +
–
ns
40
ns
18, 37
IPW
tRPA
tRPA
tRRD
tRRD
tFAW
tRP
t
t
tRP
tRP
tRP
tRP
tRP
Max Units Notes
tRP
WTR
7.5
–
7.5
–
7.5
–
7.5
–
7.5
–
7.5
–
10
–
MRD
2
–
2
–
2
–
2
–
2
–
2
–
2
–
t
CK
18
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Command and Address
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Table 11:
AC Operating Specifications and Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet 6 of 7)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported;
Notes: 1–5 (page 35) apply to the entire table; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Parameter
Refresh
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DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Table 11:
Power-Down
-25E
tREFI
–
7.8
–
7.8
–
7.8
–
7.8
–
7.8
–
7.8
–
REFIIT
–
3.9
–
3.9
–
3.9
–
3.9
–
3.9
–
3.9
–
3.9
–
3.9
–
3.9
–
3.9
–
3.9
–
3.9
75
105
127.5
197.5
tDELAY
tXSRD
tISXR
tXP
tCKE
Min
Max
75
105
127.5
197.5
Min
Max
75
105
127.5
197.5
Min
Max
75
105
127.5
197.5
Min
Max Units Notes
75
105
127.5
197.5
ns
18, 41
7.8
µs
18, 41
–
3.9
µs
18, 41
–
3.9
µs
18, 41
ns
42
MIN limit = tIS + tCK + tIH
MAX limit = n/a
MIN limit = tRFC (MIN) + 10
MAX limit = n/a
tXSNR
tXARD
Max
-5E
75
105
127.5
197.5
75
105
127.5
197.5
Min
-37E
Min
AT
Max
-3
tRFC
tREFI
Min
-3E
Symbol
t
Max
-25
MIN limit = 200
MAX limit = n/a
MIN limit = tIS
MAX limit = n/a
–
2
–
3
–
2
–
2
10 AL
–
8 - AL
–
8 - AL
–
7 - AL
3
–
2
–
2
–
2
ns
tCK
18
ps
33, 43
2
–
2
–
2
–
tCK
18
–
7 - AL
–
6 - AL
–
6 - AL
–
tCK
18
–
2
–
2
–
2
–
tCK
18
tCK
18, 44
MIN = 3
MAX = n/a
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Self Refresh
33
REFRESH- 256Mb
to512Mb
ACTIVATE 1Gb
or to2Gb
REFRESH
interval
Average periodic
refresh
(commercial)
Average periodic
refresh (industrial)
Average periodic
refresh
(automotive)
CKE LOW to CK,
CK# uncertainty
Exit SELF REFRESH
to nonREAD
command
Exit SELF REFRESH
to READ command
Exit SELF REFRESH
timing reference
Exit active MR12
power=0
down to
MR12
READ
=1
command
Exit precharge
power-down to
any nonREAD
command
CKE MIN HIGH/
LOW time
-187E
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Table 11:
AC Operating Specifications and Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet 7 of 7)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported;
Notes: 1–5 (page 35) apply to the entire table; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Parameter
-187E
ODT
-25
-3E
-3
-37E
-5E
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
tANPD
4
–
3
–
3
–
3
–
3
–
3
–
3
–
tCK
18
11
–
10
–
10
–
8
–
8
–
8
–
8
–
tCK
18
tCK
ps
18
18, 45
19, 46
ps
47, 48
ps
49
ODT to powerdown entry latency
tAXPD
ODT power-down
exit latency
ODT turn-on delay tAOND
ODT turn-off delay tAOFD
t
AON
ODT turn-on
ODT turn-off
-25E
t
t
AC
AC
(MIN) (MAX)
+ 2,575
t
AOF
tAC
MIN = tAC (MIN)
MAX = tAC (MAX) + 600
2
2.5
MIN = tAC (MIN)
MAX = tAC (MAX) + 700
Max Units Notes
tCK
MIN = tAC (MIN)
MAX = tAC (MAX) + 1,000
MIN = tAC (MIN)
MAX = tAC (MAX) + 600
MIN = tAC (MIN) + 2,000
MAX = 2 × tCK + tAC (MAX) + 1,000
tAONPD
ODT turn-off
(power-down
mode)
ODT enable from
MRS command
tAOFPD
MIN = tAC (MIN) + 2,000
MAX = 2.5 × tCK + tAC (MAX) + 1,000
ps
tMOD
MIN = 12
MAX = n/a
ns
(MIN)
+ 2,000
34
2×
+
tAC
(MAX)
+
1,000
tCK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
18, 50
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
ODT turn-on
(power-down
mode)
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
Notes
1. All voltages are referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specifications and the
operation of the device are warranted for the full voltage range specified. ODT is disabled for all measurements that are not ODT-specific.
3. Outputs measured with equivalent load (see Figure 18 on page 43).
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.0V in the test environment, and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The slew rate for the input signals used to test the
device is 1.0 V/ns for signals in the range between VIL(AC) and VIH(AC). Slew rates
other than 1.0 V/ns may require the timing parameters to be derated as specified.
5. The AC and DC input level specifications are as defined in the SSTL_18 standard (that
is, the receiver will effectively switch as a result of the signal crossing the AC input
level and will remain in that state as long as the signal does not ring back above
[below] the DC input LOW [HIGH] level).
6. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measured differentially).
7. Operating frequency is only allowed to change during self refresh mode (see Figure 81
on page 114), precharge power-down mode, or system reset condition (see "RESET"
on page 115). SSC allows for small deviations in operating frequency, provided the
SSC guidelines are satisfied.
8. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and
tCK (AVG) MIN is the smallest clock rate allowed (except for a deviation due to
allowed clock jitter). Input clock jitter is allowed provided it does not exceed values
specified. Also, the jitter must be of a random Gaussian distribution in nature.
9. Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread spectrum at a sweep rate in the range 20–60 KHz with
an additional one percent tCK (AVG); however, the spread spectrum may not use a
clock rate below tCK (AVG) MIN or above tCK (AVG) MAX.
10. MIN (tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock
HIGH time driven to the device. The clock’s half period must also be of a Gaussian distribution; tCH (AVG) and tCL (AVG) must be met with or without clock jitter and with
or without duty cycle jitter. tCH (AVG) and tCL (AVG) are the average of any 200 consecutive CK falling edges.
11. tHP (MIN) is the lesser of tCL and tCH actually applied to the device CK and CK#
inputs; thus, tHP (MIN) ≥ the lesser of tCL (ABS) MIN and tCH (ABS) MIN.
12. The period jitter (tJITPER) is the maximum deviation in the clock period from the average or nominal clock allowed in either the positive or negative direction. JEDEC specifies tighter jitter numbers during DLL locking time. During DLL lock time, the jitter
values should be 20 percent less those than noted in the table (DLL locked).
13. The half-period jitter (tJITDTY) applies to either the high pulse of clock or the low
pulse of clock; however, the two cumulatively can not exceed tJITPER.
14. The cycle-to-cycle jitter (tJITCC) is the amount the clock period can deviate from one
cycle to the next. JEDEC specifies tighter jitter numbers during DLL locking time.
During DLL lock time, the jitter values should be 20 percent less than those noted in
the table (DLL locked).
15. The cumulative jitter error (tERRnPER), where n is 2, 3, 4, 5, 6–10, or 11–50 is the
amount of clock time allowed to consecutively accumulate away from the average
clock over any number of clock cycles.
16. JEDEC specifies using tERR6–10PER when derating clock-related output timing (see
notes 19 and 48). Micron requires less derating by allowing tERR5PER to be used.
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DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
17. This parameter is not referenced to a specific voltage level but is specified when the
device output is no longer driving (tRPST) or beginning to drive (tRPRE).
18. The inputs to the DRAM must be aligned to the associated clock, that is, the actual
clock that latches it in. However, the input timing (in ns) references to the tCK (AVG)
when determining the required number of clocks. The following input parameters are
determined by taking the specified percentage times the tCK (AVG) rather than tCK:
t
IPW, tDIPW, tDQSS, tDQSH, tDQSL, tDSS, tDSH, tWPST, and tWPRE.
19. The DRAM output timing is aligned to the nominal or average clock. Most output
parameters must be derated by the actual jitter error when input clock jitter is
present; this will result in each parameter becoming larger. The following parameters
are required to be derated by subtracting tERR5PER (MAX): tAC (MIN), tDQSCK (MIN),
t
LZDQS (MIN), tLZDQ (MIN), tAON (MIN); while the following parameters are required
to be derated by subtracting tERR5PER (MIN): tAC (MAX), tDQSCK (MAX), tHZ (MAX),
t
LZDQS (MAX), tLZDQ (MAX), tAON (MAX). The parameter tRPRE (MIN) is derated by
subtracting tJITPER (MAX), while tRPRE (MAX), is derated by subtracting
t
JITPER (MIN). The parameter tRPST (MIN) is derated by subtracting tJITDTY (MAX),
while tRPST (MAX), is derated by subtracting tJITDTY (MIN). Output timings that
require tERR5PER derating can be observed to have offsets relative to the clock; however, the total window will not degrade.
20. When DQS is used single-ended, the minimum limit is reduced by 100ps.
21. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (tHZ) or begins driving (tLZ).
22. tLZ (MIN) will prevail over a tDQSCK (MIN) + tRPRE (MAX) condition.
23. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
24. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no
WRITEs were previously in progress on the bus. If a previous WRITE was in progress,
DQS could be HIGH during this time, depending on tDQSS.
25. The intent of the “Don’t Care” state after completion of the postamble is that the DQSdriven signal should either be HIGH, LOW, or High-Z, and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions HIGH (above VIH[DC] MIN), then it must not transition LOW (below
VIH[DC]) prior to tDQSH (MIN).
26. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with DQ0–DQ7;
x16 = LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.
27. The data valid window is derived by achieving other specifications: tHP (tCK/2),
tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived.
28. tQH = tHP - tQHS; the worst case tQH would be the lesser of tCL (ABS) MAX or
tCH (ABS) MAX times tCK (ABS) MIN - tQHS. Minimizing the amount of tCH (AVG)
offset and value of tJITDTY will provide a larger tQH, which in turn will provide a larger
valid data out window.
29. This maximum value is derived from the referenced test load. tHZ (MAX) will prevail
over tDQSCK (MAX) + tRPST (MAX) condition.
30. The values listed are for the differential DQS strobe (DQS and DQS#) with a differential slew rate of 2 V/ns (1 V/ns for each signal). There are two sets of values listed: tDSa,
tDH and tDS , tDH . The tDS , tDH values (for reference only) are equivalent to the
a
b
b
a
a
baseline values of tDSb, tDHb at VREF when the slew rate is 2 V/ns, differentially. The
baseline values, tDSb, tDHb, are the JEDEC-defined values, referenced from the logic
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AC Timing Operating Specifications
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
trip points. tDSb is referenced from VIH(AC) for a rising signal and VIL(AC) for a falling
signal, while tDHb is referenced from VIL(DC) for a rising signal and VIH(DC) for a falling signal. If the differential DQS slew rate is not equal to 2 V/ns, then the baseline values must be derated by adding the values from Tables 30 and 31 on pages 55–56. If the
DQS differential strobe feature is not enabled, then the DQS strobe is single-ended
and the baseline values must be derated using Table 32 on page 57. Single-ended DQS
data timing is referenced at DQS crossing VREF. The correct timing values for a singleended DQS strobe are listed in Tables 33–35 on pages 57–58; listed values are already
derated for slew rate variations and converted from baseline values to VREF values.
VIL/VIH DDR2 overshoot/undershoot. See “AC Overshoot/Undershoot Specification”
on page 49.
For each input signal—not the group collectively.
There are two sets of values listed for command/address: tISa, tIHa and tISb, tIHb. The
t
ISa, tIHa values (for reference only) are equivalent to the baseline values of tISb, tIHb
at VREF when the slew rate is 1 V/ns. The baseline values, tISb, tIHb, are the JEDECdefined values, referenced from the logic trip points. tISb is referenced from VIH(AC)
for a rising signal and VIL(AC) for a falling signal, while tIHb is referenced from VIL(DC)
for a rising signal and VIH(DC) for a falling signal. If the command/address slew rate is
not equal to 1 V/ns, then the baseline values must be derated by adding the values
from Tables 28 and 29 on page 52.
This is applicable to READ cycles only. WRITE cycles generally require additional time
due to tWR during auto precharge.
READs and WRITEs with auto precharge are allowed to be issued before tRAS (MIN) is
satisfied because tRAS lockout feature is supported in DDR2 SDRAM.
When a single-bank PRECHARGE command is issued, tRP timing applies. tRPA timing
applies when the PRECHARGE (ALL) command is issued, regardless of the number of
banks open. For 8-bank devices (≥1Gb), tRPA (MIN) = tRP (MIN) + tCK (AVG) (Table 11
on page 28 lists tRP [MIN] + tCK [AVG] MIN).
This parameter has a two clock minimum requirement at any tCK.
The tFAW (MIN) parameter applies to all 8-bank DDR2 devices. No more than four
bank-ACTIVATE commands may be issued in a given tFAW (MIN) period. tRRD (MIN)
restriction still applies.
The minimum internal READ-to-PRECHARGE time. This is the time from which the
last 4-bit prefetch begins to when the PRECHARGE command can be issued. A 4-bit
prefetch is when the READ command internally latches the READ so that data will
output CL later. This parameter is only applicable when tRTP/(2 × tCK) > 1, such as
frequencies faster than 533 MHz when tRTP = 7.5ns. If tRTP/(2 × tCK) ≤ 1, then equation AL + BL/2 applies. tRAS (MIN) has to be satisfied as well. The DDR2 SDRAM will
automatically delay the internal PRECHARGE command until tRAS (MIN) has been
satisfied.
tDAL = (nWR) + (tRP/tCK). Each of these terms, if not already an integer, should be
rounded up to the next integer. tCK refers to the application clock period; nWR refers
to the tWR parameter stored in the MR9–MR11 For example, -37E at tCK = 3.75ns with
tWR programmed to four clocks would have tDAL = 4 + (15ns/3.75ns) clocks =
4 + (4) clocks = 8 clocks.
The refresh period is 64ms (commercial) or 32ms (industrial and automotive). This
equates to an average refresh rate of 7.8125µs (commercial) or 3.9607µs (industrial
and automotive). To ensure all rows of all banks are properly refreshed, 8,192
REFRESH commands must be issued every 64ms (commercial) or 32ms (industrial
and automotive). The JEDEC tRFC MAX of 70,000ns is not required as bursting of
AUTOREFRESH commands is allowed.
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AC and DC Operating Conditions
42. tDELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed
prior to CK, CK# being removed in a system RESET condition (see "RESET" on page
115).
t
43. ISXR is equal to tIS and is used for CKE setup time during self refresh exit, as shown in
Figure 71 on page 106.
44. tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to
achieve the three clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of tIS + 2 × tCK + tIH.
45. The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock
value must be derated by the amount of half-clock duty cycle error. For example, if the
clock duty cycle was 47/53, tAOFD would actually be 2.5 - 0.03, or 2.47, for tAOF (MIN)
and 2.5 + 0.03, or 2.53, for tAOF (MAX).
46. ODT turn-on time tAON (MIN) is when the device leaves High-Z and ODT resistance
begins to turn on. ODT turn-on time tAON (MAX) is when the ODT resistance is fully
on. Both are measured from tAOND.
47. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance.
ODT turn off time tAOF (MAX) is when the bus is in High-Z. Both are measured from
t
AOFD.
48. Half-clock output parameters must be derated by the actual tERR5PER and tJITDTY
when input clock jitter is present; this will result in each parameter becoming larger.
The parameter tAOF (MIN) is required to be derated by subtracting both
t
ERR5PER (MAX) and tJITDTY (MAX). The parameter tAOF (MAX) is required to be derated by subtracting both tERR5PER (MIN) and tJITDTY (MIN).
49. The -187E maximum limit is 2 × tCK + tAC (MAX) + 1,000 but it will likely be
3 x tCK + tAC (MAX) + 1,000 in the future.
50. Should use 8 tCK for backward compatibility.
AC and DC Operating Conditions
Table 12:
Recommended DC Operating Conditions (SSTL_18)
All voltages referenced to VSS
Parameter
Symbol
Min
Nom
Max
Units
Notes
Supply voltage
VDDL supply voltage
I/O supply voltage
I/O reference voltage
I/O termination voltage (system)
VDD
VDDL
VDDQ
VREF(DC)
VTT
1.7
1.7
1.7
0.49 × VDDQ
VREF(DC) - 40
1.8
1.8
1.8
0.50 × VDDQ
VREF(DC)
1.9
1.9
1.9
0.51 × VDDQ
VREF(DC) + 40
V
V
V
V
mV
1, 2
2, 3
2, 3
4
5
Notes:
VDD and VDDQ must track each other. VDDQ must be ≤ VDD.
VSSQ = VSSL = VSS.
VDDQ tracks with VDD; VDDL tracks with VDD.
VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the
DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed ±1
percent of the DC value. Peak-to-peak AC noise on VREF may not exceed ±2 percent of
VREF(DC). This measurement is to be taken at the nearest VREF bypass capacitor.
5. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF.
1.
2.
3.
4.
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ODT DC Electrical Characteristics
ODT DC Electrical Characteristics
Table 13:
ODT DC Electrical Characteristics
All voltages are referenced to VSS
Parameter
Symbol
Min
Nom
Max
Units
Notes
RTT effective impedance value for 75Ω setting
EMR (A6, A2) = 0, 1
RTT effective impedance value for 150Ω setting
EMR (A6, A2) = 1, 0
RTT effective impedance value for 50Ω setting
EMR (A6, A2) = 1, 1
Deviation of VM with respect to VDDQ/2
RTT1(EFF)
60
75
90
Ω
1, 2
RTT2(EFF)
120
150
180
Ω
1, 2
RTT3(EFF)
40
50
60
Ω
1, 2
ΔVM
–6
6
%
3
Notes:
1. RTT1(EFF) and RTT2(EFF) are determined by separately applying VIH(AC) and VIL(AC) to the ball
being tested, and then measuring current, I(VIH(AC)), and I(VIL(AC)), respectively.
(EQ 1)
V IH ( AC ) – V IL ( AC )
R TT ( EFF ) = ------------------------------------------------------------I ( V IH ( AC ) ) – I ( V IL ( AC ) )
2. Minimum IT and AT device values are derated by six percent when the devices operate
between –40°C and 0°C (TC).
3. Measure voltage (VM) at tested ball with no load.
(EQ 2)
2 × VM
ΔVM = ⎛⎝ ------------------ – 1⎞⎠ × 100
V DD Q
Input Electrical Characteristics and Operating Conditions
Table 14:
Input DC Logic Levels
All voltages are referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Input high (logic 1) voltage
Input low (logic 0) voltage
Notes:
Table 15:
Min
VREF(DC) + 125
–300
Max
1
Units
VDDQ
VREF(DC) - 125
mV
mV
Min
Max
Units
VREF(DC) + 250
VREF(DC) + 200
–300
–300
VDDQ1
VDDQ1
mV
mV
mV
mV
1. VDDQ + 300mV allowed provided 1.9V is not exceeded.
Input AC Logic Levels
All voltages referenced to VSS
Parameter
Symbol
Input high (logic 1) voltage (-37E/-5E)
Input high (logic 1) voltage (-187E/-25E/-25/-3E/-3)
Input low (logic 0) voltage (-37E/-5E)
Input low (logic 0) voltage (-187E/-25E/-25/-3E/-3)
Notes:
VIH(AC)
VIH(AC)
VIL(AC)
VIL(AC)
VREF(DC) - 250
VREF(DC) - 200
1. VDDQ + 300mV allowed provided 1.9V is not exceeded.
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Input Electrical Characteristics and Operating Conditions
Figure 15:
Single-Ended Input Signal Levels
Notes:
1,150mV
VIH(AC)
1,025mV
VIH(DC)
936mV
918mV
900mV
882mV
864mV
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
775mV
VIL(DC)
650mV
VIL(AC)
1. Numbers in diagram reflect nominal DDR2-400/DDR2-533 values.
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Input Electrical Characteristics and Operating Conditions
Table 16:
Differential Input Logic Levels
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Units
Notes
DC input signal voltage
DC differential input voltage
AC differential input voltage
AC differential cross-point voltage
Input midpoint voltage
VIN(DC)
VID(DC)
VID(AC)
VIX(AC)
VMP(DC)
–300
250
500
0.50 × VDDQ - 175
850
VDDQ
VDDQ
VDDQ
0.50 × VDDQ + 175
950
mV
mV
mV
mV
mV
1, 6
2, 6
3, 6
4
5
Notes:
Figure 16:
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK,
CK#, DQS, DQS#, LDQS, LDQS#, UDQS, UDQS#, and RDQS, RDQS#.
2. VID(DC) specifies the input differential voltage |VTR - VCP| required for switching, where VTR
is the true input (such as CK, DQS, LDQS, UDQS) level and VCP is the complementary input
(such as CK#, DQS#, LDQS#, UDQS#) level. The minimum value is equal to VIH(DC) - VIL(DC).
Differential input signal levels are shown in Figure 16.
3. VID(AC) specifies the input differential voltage |VTR - VCP| required for switching, where VTR
is the true input (such as CK, DQS, LDQS, UDQS, RDQS) level and VCP is the complementary
input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#) level. The minimum value is equal to
VIH(AC) - VIL(AC), as shown in Table 15 on page 39.
4. The typical value of VIX(AC) is expected to be about 0.5 × VDDQ of the transmitting device
and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which
differential input signals must cross, as shown in Figure 16.
5. VMP(DC) specifies the input differential common mode voltage (VTR + VCP)/2 where VTR is
the true input (CK, DQS) level and VCP is the complementary input (CK#, DQS#). VMP(DC) is
expected to be approximately 0.5 × VDDQ.
6. VDDQ + 300mV allowed provided 1.9V is not exceeded.
Differential Input Signal Levels
VIN(DC) MAX1
2.1V
VDDQ = 1.8V
CP2
X
1.075V
VMP(DC)3 VIX(AC)4
0.9V
0.725V
VID(DC)5
VID(AC)6
X
TR2
VIN(DC) MIN1
–0.30V
Notes:
1. TR and CP may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.
2. TR represents the CK, DQS, RDQS, LDQS, and UDQS signals; CP represents CK#, DQS#,
RDQS#, LDQS#, and UDQS# signals.
3. This provides a minimum of 850mV to a maximum of 950mV and is expected to be VDDQ/2.
4. TR and CP must cross in this region.
5. TR and CP must meet at least VID(DC) MIN when static and is centered around VMP(DC).
6. TR and CP must have a minimum 500mV peak-to-peak swing.
7. Numbers in diagram reflect nominal values (VDDQ = 1.8V).
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Output Electrical Characteristics and Operating Conditions
Output Electrical Characteristics and Operating Conditions
Table 17:
Differential AC Output Parameters
Parameter
Symbol
Min
Max
Units
Notes
AC differential cross-point voltage
AC differential voltage swing
VOX(AC)
VSWING
0.50 × VDDQ - 125
1.0
0.50 × VDDQ + 125
mV
mV
1
Notes:
Figure 17:
1. The typical value of VOX(AC) is expected to be about 0.5 × VDDQ of the transmitting device
and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at which
differential output signals must cross.
Differential Output Signal Levels
VDDQ
VTR
Crossing point
VSWING
VOX
VCP
VSSQ
Table 18:
Output DC Current Drive
Parameter
Output MIN source DC current
Output MIN sink DC current
Notes:
Symbol
Value
Units
Notes
IOH
IOL
–13.4
13.4
mA
mA
1, 2, 4
2, 3, 4
1. For IOH(DC); VDDQ = 1.7V, VOUT = 1,420mV. (VOUT - VDDQ)/IOH must be less than 21Ω for values of VOUT between VDDQ and VDDQ - 280mV.
2. For IOL(DC); VDDQ = 1.7V, VOUT = 280mV. VOUT/IOL must be less than 21Ω for values of VOUT
between 0V and 280mV.
3. The DC value of VREF applied to the receiving device is set to VTT.
4. The values of IOH(DC) and IOL(DC) are based on the conditions given in Notes 1 and 2. They
are used to test device drive current capability to ensure VIH (MIN) plus a noise margin and
VIL (MAX) minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see output IV curves) along a
21Ω load line to define a convenient driver current for measurement.
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Output Electrical Characteristics and Operating Conditions
Table 19:
Output Characteristics
Parameter
Min
Pull-up and pull-down mismatch
Output slew rate
Figure 18:
Max
See “Output Driver Characteristics” on
page 44
0
4
1.5
5
Output impedance
Notes:
Nom
Units
Notes
Ω
1, 2
Ω
V/ns
1, 2, 3
1, 4, 5, 6
1. Absolute specifications: 0°C ≤ TC ≤ +85°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V.
2. Impedance measurement conditions for output source DC current: VDDQ = 1.7V;
VOUT = 1,420mV; (VOUT - VDDQ)/IOH must be less than 23.4Ω for values of VOUT between
VDDQ and VDDQ - 280mV. The impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4Ω for values of VOUT
between 0V and 280mV.
3. Mismatch is an absolute value between pull-up and pull-down; both are measured at the
same temperature and voltage.
4. Output slew rate for falling and rising edges is measured between VTT - 250mV and
VTT + 250mV for single-ended signals. For differential signals (DQS, DQS#), output slew rate
is measured between DQS - DQS# = –500mV and DQS# - DQS = +500mV. Output slew rate is
guaranteed by design but is not necessarily tested on each device.
5. The absolute value of the slew rate as measured from VIL(DC) MAX to VIH(DC) MIN is equal to
or greater than the slew rate as measured from VIL(AC) MAX to VIH(AC) MIN. This is guaranteed by design and characterization.
6. IT and AT devices require an additional 0.4 V/ns in the MAX limit when TC is between –40°C
and 0°C.
Output Slew Rate Load
VTT = VDDQ/2
Output
(VOUT)
25Ω
Reference
point
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Output Driver Characteristics
Output Driver Characteristics
Figure 19:
Full Strength Pull-Down Characteristics
120
100
IOUT (MA)
80
60
40
20
0
0.0
0.5
1.0
1.5
VOUT (V)
Table 20:
Full Strength Pull-Down Current (mA)
Voltage (V)
Min
Nom
Max
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
0.00
4.30
8.60
12.90
16.90
20.40
23.28
25.44
26.79
27.67
28.38
28.96
29.46
29.90
30.29
30.65
30.98
31.31
31.64
31.96
0.00
5.63
11.30
16.52
22.19
27.59
32.39
36.45
40.38
44.01
47.01
49.63
51.71
53.32
54.9
56.03
57.07
58.16
59.27
60.35
0.00
7.95
15.90
23.85
31.80
39.75
47.70
55.55
62.95
69.55
75.35
80.35
84.55
87.95
90.70
93.00
95.05
97.05
99.05
101.05
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Output Driver Characteristics
Figure 20:
Full Strength Pull-Up Characteristics
0
–20
IOUT (mA)
–40
–60
–80
–100
–120
0
0.5
1.0
1.5
VDDQ - VOUT (V)
Table 21:
Full Strength Pull-Up Current (mA)
Voltage (V)
Min
Nom
Max
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
0.00
–4.30
–8.60
–12.90
–16.90
–20.40
–23.28
–25.44
–26.79
–27.67
–28.38
–28.96
–29.46
–29.90
–30.29
–30.65
–30.98
–31.31
–31.64
–31.96
0.00
–5.63
–11.30
–16.52
–22.19
–27.59
–32.39
–36.45
–40.38
–44.01
–47.01
–49.63
–51.71
–53.32
–54.90
–56.03
–57.07
–58.16
–59.27
–60.35
0.00
–7.95
–15.90
–23.85
–31.80
–39.75
–47.70
–55.55
–62.95
–69.55
–75.35
–80.35
–84.55
–87.95
–90.70
–93.00
–95.05
–97.05
–99.05
–101.05
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512Mb: x4, x8, x16 DDR2 SDRAM
Output Driver Characteristics
Figure 21:
Reduced Strength Pull-Down Characteristics
70
60
IOUT (mV)
50
40
30
20
10
0
0.0
0.5
1.0
1.5
VOUT (V)
Table 22:
Reduced Strength Pull-Down Current (mA)
Voltage (V)
Min
Nom
Max
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
0.00
1.72
3.44
5.16
6.76
8.16
9.31
10.18
10.72
11.07
11.35
11.58
11.78
11.96
12.12
12.26
12.39
12.52
12.66
12.78
0.00
2.98
5.99
8.75
11.76
14.62
17.17
19.32
21.40
23.32
24.92
26.30
27.41
28.26
29.10
29.70
30.25
30.82
31.41
31.98
0.00
4.77
9.54
14.31
19.08
23.85
28.62
33.33
37.77
41.73
45.21
48.21
50.73
52.77
54.42
55.80
57.03
58.23
59.43
60.63
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512Mb: x4, x8, x16 DDR2 SDRAM
Output Driver Characteristics
Figure 22:
Reduced Strength Pull-Up Characteristics
0
–10
IOUT (mV)
–20
–30
–40
–50
–60
–70
0.0
0.5
1.0
1.5
VDDQ - VOUT (V)
Table 23:
Reduced Strength Pull-Up Current (mA)
Voltage (V)
Min
Nom
Max
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
0.00
–1.72
–3.44
–5.16
–6.76
–8.16
–9.31
–10.18
–10.72
–11.07
–11.35
–11.58
–11.78
–11.96
–12.12
–12.26
–12.39
–12.52
–12.66
–12.78
0.00
–2.98
–5.99
–8.75
–11.76
–14.62
–17.17
–19.32
–21.40
–23.32
–24.92
–26.30
–27.41
–28.26
–29.10
–29.69
–30.25
–30.82
–31.42
–31.98
0.00
–4.77
–9.54
–14.31
–19.08
–23.85
–28.62
–33.33
–37.77
–41.73
–45.21
–48.21
–50.73
–52.77
–54.42
–55.8
–57.03
–58.23
–59.43
–60.63
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512Mb: x4, x8, x16 DDR2 SDRAM
Power and Ground Clamp Characteristics
Power and Ground Clamp Characteristics
Power and ground clamps are provided on the following input-only balls: Address balls,
bank address balls, CS#, RAS#, CAS#, WE#, ODT, and CKE.
Table 24:
Input Clamp Characteristics
Voltage Across Clamp
(V)
Minimum Power Clamp Current
(mA)
Minimum Ground Clamp Current
(mA)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.1
1.0
2.5
4.7
6.8
9.1
11.0
13.5
16.0
18.2
21.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.1
1.0
2.5
4.7
6.8
9.1
11.0
13.5
16.0
18.2
21.0
Figure 23:
Input Clamp Characteristics
Minimum Clamp Current (mA)
25
20
15
10
5
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
Voltage Across Clamp (V)
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512Mb: x4, x8, x16 DDR2 SDRAM
AC Overshoot/Undershoot Specification
AC Overshoot/Undershoot Specification
Some revisions will support the 0.9V maximum average amplitude instead of the 0.5V
maximum average amplitude shown in Tables 25 and 26.
Table 25:
Address and Control Balls
Applies to address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE, ODT
Specification
Parameter
-187E
-25/-25E
-3/-3E
-37E
-5E
Maximum peak amplitude allowed for overshoot area (see
Figure 24)
Maximum peak amplitude allowed for undershoot area
(see Figure 25)
Maximum overshoot area above VDD (see Figure 24)
Maximum undershoot area below VSS (see Figure 25)
0.50V
0.50V
0.50V
0.50V
0.50V
0.50V
0.50V
0.50V
0.50V
0.50V
0.5 Vns
0.5 Vns
0.66 Vns
0.66 Vns
0.80 Vns
0.80 Vns
1.00 Vns
1.00 Vns
1.33 Vns
1.33 Vns
Table 26:
Clock, Data, Strobe, and Mask Balls
Applies to DQ, DQS, DQS#, RDQS, RDQS#, UDQS, UDQS#, LDQS, LDQS#, DM, UDM, LDM
Specification
Parameter
-187E
-25/-25E
-3/-3E
-37E
-5E
Maximum peak amplitude allowed for overshoot area (see
Figure 24)
Maximum peak amplitude allowed for undershoot area
(see Figure 25)
Maximum overshoot area above VDDQ (see Figure 24)
Maximum undershoot area below VSSQ (see Figure 25)
0.50V
0.50V
0.50V
0.50V
0.50V
0.50V
0.50V
0.50V
0.50V
0.50V
0.19 Vns
0.19 Vns
0.23 Vns
0.23 Vns
0.23 Vns
0.23 Vns
0.28 Vns
0.28 Vns
0.38 Vns
0.38 Vns
Figure 24:
Overshoot
Maximum amplitude
VOLTS (V)
Overshoot area
VDD/VDDQ
VSS/VSSQ
Figure 25:
Time (ns)
Undershoot
Volts (V)
VSS/VSSQ
Undershoot area
Maximum amplitude
Time (ns)
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512Mb: x4, x8, x16 DDR2 SDRAM
AC Overshoot/Undershoot Specification
Table 27:
AC Input Test Conditions
Parameter
Symbol
Input setup timing measurement reference level address
balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT, DM,
UDM, LDM, and CKE
Input hold timing measurement reference level address
balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT, DM,
UDM, LDM, and CKE
Input timing measurement reference level (single-ended)
DQS for x4, x8; UDQS, LDQS for x16
Input timing measurement reference level (differential)
CK, CK# for x4, x8, x16; DQS, DQS# for x4, x8; RDQS,
RDQS# for x8; UDQS, UDQS#, LDQS, LDQS# for x16
Notes:
Min
Max
Units
Notes
VRS
See Note 2
1, 2, 3,
4
VRH
See Note 5
1, 3, 4,
5
VREF(DC)
VDDQ × 0.49 VDDQ × 0.51
V
VRD
VIX(AC)
V
1, 3, 4,
6
1, 3, 7,
8, 9
1. All voltages referenced to VSS.
2. Input waveform setup timing (tISb) is referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under
test, as shown in Figure 34 on page 61.
3. See “Input Slew Rate Derating” on page 51.
4. The slew rate for single-ended inputs is measured from DC level to AC level, VIL(DC) to
VIH(AC) on the rising edge and VIL(AC) to VIH(DC) on the falling edge. For signals referenced
to VREF, the valid intersection is where the “tangent” line intersects VREF, as shown in
Figures 27, 29, 31, and 33.
5. Input waveform hold (tIHb) timing is referenced from the input signal crossing at the VIL(DC)
level for a rising signal and VIH(DC) for a falling signal applied to the device under test, as
shown in Figure 34 on page 61.
6. Input waveform setup timing (tDS) and hold timing (tDH) for single-ended data strobe is
referenced from the crossing of DQS, UDQS, or LDQS through the VREF level applied to the
device under test, as shown in Figure 36 on page 62.
7. Input waveform setup timing (tDS) and hold timing (tDH) when differential data strobe is
enabled is referenced from the cross-point of DQS/DQS#, UDQS/UDQS#, or LDQS/LDQS#, as
shown in Figure 35 on page 61.
8. Input waveform timing is referenced to the crossing point level (VIX) of two input signals
(VTR and VCP) applied to the device under test, where VTR is the true input signal and VCP is
the complementary input signal, as shown in Figure 37 on page 62.
9. The slew rate for differentially ended inputs is measured from twice the DC level to twice
the AC level: 2 × VIL(DC) to 2 × VIH(AC) on the rising edge and 2 × VIL(AC) to 2 × VIH(DC) on the
falling edge. For example, the CK/CK# would be –250mV to +500mV for CK rising edge and
would be +250mV to –500mV for CK falling edge.
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Input Slew Rate Derating
Input Slew Rate Derating
For all input signals, the total tIS (setup time) and tIH (hold time) required is calculated
by adding the data sheet tIS (base) and tIH (base) value to the ΔtIS and ΔtIH derating
value, respectively. Example: tIS (total setup time) = tIS (base) + ΔtIS.
tIS, the nominal slew rate for a rising signal, is defined as the slew rate between the last
crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup nominal slew rate (tIS)
for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and
the first crossing of VIL(AC) MAX.
If the actual signal is always earlier than the nominal slew rate line between shaded
“VREF(DC) to AC region,” use the nominal slew rate for the derating value (Figure 26 on
page 53).
If the actual signal is later than the nominal slew rate line anywhere between the shaded
“VREF(DC) to AC region,” the slew rate of a tangent line to the actual signal from the AC
level to DC level is used for the derating value (see Figure 27 on page 53).
tIH, the nominal slew rate for a rising signal, is defined as the slew rate between the last
crossing of VIL(DC) MAX and the first crossing of VREF(DC). tIH, nominal slew rate for a
falling signal, is defined as the slew rate between the last crossing of VIH(DC) MIN and
the first crossing of VREF(DC).
If the actual signal is always later than the nominal slew rate line between shaded “DC to
VREF(DC) region,” use the nominal slew rate for the derating value (Figure 28 on page 54).
If the actual signal is earlier than the nominal slew rate line anywhere between shaded
“DC to VREF(DC) region,” the slew rate of a tangent line to the actual signal from the DC
level to VREF(DC) level is used for the derating value (Figure 29 on page 54).
Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid
input signal is still required to complete the transition and reach VIH(AC)/VIL(AC).
For slew rates in between the values listed in Tables 28 and 29 on page 52, the derating
values may obtained by linear interpolation.
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Input Slew Rate Derating
Table 28:
DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH)
CK, CK# Differential Slew Rate
Command/
Address Slew
Rate (V/ns)
t
Δ IS
t
Δ IH
t
Δ IS
t
Δ IH
t
Δ IS
ΔtIH
Units
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
+187
+179
+167
+150
+125
+83
0
–11
–25
–43
–67
–110
–175
–285
–350
–525
–800
–1,450
+94
+89
+83
+75
+45
+21
0
–14
–31
–54
–83
–125
–188
–292
–375
–500
–708
–1,125
+217
+209
+197
+180
+155
+113
+30
+19
+5
–13
–37
–80
–145
–255
–320
–495
–770
–1,420
+124
+119
+113
+105
+75
+51
+30
+16
–1
–24
–53
–95
–158
–262
–345
–470
–678
–1,095
+247
+239
+227
+210
+185
+143
+60
+49
+35
+17
–7
–50
–115
–225
–290
–465
–740
–1,390
+154
+149
+143
+135
+105
+81
+60
+46
+29
+6
–23
–65
–128
–232
–315
–440
–648
–1,065
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Table 29:
2.0 V/ns
1.5 V/ns
1.0 V/ns
DDR2-667/800/1066 Setup and Hold Time Derating Values (tIS and tIH)
CK, CK# Differential Slew Rate
Command/
Address Slew
Rate (V/ns)
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
Units
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
+150
+143
+133
+120
+100
+67
0
–5
–13
–22
–34
–60
–100
–168
–200
–325
–517
–1,000
+94
+89
+83
+75
+45
+21
0
–14
–31
–54
–83
–125
–188
–292
–375
–500
–708
–1,125
+180
+173
+163
+150
+160
+97
+30
+25
+17
+8
–4
–30
–70
–138
–170
–295
–487
–970
+124
+119
+113
+105
+75
+51
+30
+16
–1
–24
–53
–95
–158
–262
–345
–470
–678
–1,095
+210
+203
+193
+180
+160
+127
+60
+55
+47
+38
+36
0
–40
–108
–140
–265
–457
–940
+154
+149
+143
+135
+105
+81
+60
+46
+29
+6
–23
–65
–128
–232
–315
–440
–648
–1,065
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
2.0 V/ns
1.5 V/ns
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1.0 V/ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 26:
Nominal Slew Rate for tIS
CK
CK#
tIH
tIS
VDDQ
tIS
tIH
VIH(AC) MIN
VREF to AC
region
VIH(DC) MIN
Nominal
slew rate
VREF(DC)
Nominal
slew rate
VIL(DC) MAX
VREF to AC
region
VIL(AC) MAX
VSS
DTF
DTR
VREF(DC) - VIL(AC) MAX
Setup slew rate
=
falling signal
ΔTF
Figure 27:
Setup slew rate
VIH(AC) MIN - VREF(DC)
=
rising signal
ΔTR
Tangent Line for tIS
CK
CK#
tIH
tIS
VDDQ
tIS
tIH
VIH(AC) MIN
VREF to AC
region
Nominal
line
VIH(DC) MIN
Tangent
line
VREF(DC)
Tangent
line
VIL(DC) MAX
Nominal
line
VREF to AC
region
VIL(AC) MAX
ΔTF
ΔTR
VSS
Setup slew rate
Tangent line (VIH[AC] MIN - VREF[DC])
=
rising signal
ΔTR
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Input Slew Rate Derating
Figure 28:
Nominal Slew Rate for tIH
CK
CK#
tIS
tIS
tIH
tIH
VDDQ
VIH(AC) MIN
VIH(DC) MIN
DC to VREF
region
Nominal
slew rate
VREF(DC)
Nominal
slew rate
DC to VREF
region
VIL(DC) MAX
VIL(AC) MAX
VSS
ΔTF
ΔTR
Figure 29:
Tangent Line for tIH
CK
CK#
tIS
tIS
tIH
tIH
VDDQ
VIH(AC) MIN
Nominal
line
VIH(DC) MIN
DC to VREF
region
Tangent
line
VREF(DC)
Tangent
line
Nominal
line
DC to VREF
region
VIL(DC) MAX
VIL(AC) MAX
VSS
ΔTR
ΔTF
Tangent line (VREF[DC] - VIL[DC] MAX) Hold slew rate Tangent line (VIH[DC] MIN - VREF[DC])
Hold slew rate
=
=
rising signal
falling signal
ΔTF
ΔTR
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Input Slew Rate Derating
DDR2-400/DDR2-533 tDS, tDH Derating Values with Differential Strobe
Table 30:
All units are shown in picoseconds
DQS, DQS# Differential Slew Rate
DQ
Slew
Rate
(V/ns)
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
4.0 V/ns
Δ
DS
t
125
83
0
–
–
–
–
–
–
3.0 V/ns
t
t
Δ
DH
t
t
Δ
DH
t
45
21
0
–
–
–
–
–
–
125
83
0
–11
–
–
–
–
–
45
21
0
–14
–
–
–
–
–
125
83
0
–11
–25
–
–
–
–
45
21
0
–14
–31
–
–
–
–
–
95
12
1
–13
–31
–
–
–
Notes:
Δ
DS
1.8 V/ns
Δ
DH
t
Δ
DS
2.0 V/ns
Δ
DS
1.6 V/ns
t
Δ
DH
t
Δ
DS
–
33
12
–2
–19
–42
–
–
–
–
–
24
13
–1
–19
–43
–
–
1.4 V/ns
Δ
DS
Δ
DH
1.0 V/ns
t
t
Δ
DH
t
–
–
24
10
–7
–30
–59
–
–
–
–
–
25
11
–7
–31
–74
–
–
–
–
22
5
–18
–47
–89
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
23
17
–
–
–
–
5
–6
17
6
–
–
–19 –35
–7
–23
5
–11
–62 –77 –50 –65 –38 –53
–127 –140 –115 –128 –103 –116
t
Δ
DS
t
Δ
DH
0.8 V/ns
Δ
DH
t
Δ
DS
1.2 V/ns
t
Δ
DS
t
Δ
DH
t
1. For all input signals, the total tDS and tDH required is calculated by adding the data sheet
value to the derating value listed in Table 30.
2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last crossing
of VREF(DC) and the first crossing of VIH(AC) MIN. tDS nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VREF(DC) and the first crossing of
VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between
the shaded “VREF(DC) to AC region,” use the nominal slew rate for the derating value (see
Figure 30 on page 59). If the actual signal is later than the nominal slew rate line anywhere
between the shaded “VREF(DC) to AC region,” the slew rate of a tangent line to the actual
signal from the AC level to DC level is used for the derating value (see Figure 31 on
page 59).
3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF(DC). tDH nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing
of VREF (DC). If the actual signal is always later than the nominal slew rate line between the
shaded “DC level to VREF(DC) region,” use the nominal slew rate for the derating value (see
Figure 32 on page 60). If the actual signal is earlier than the nominal slew rate line anywhere between shaded “DC to VREF(DC) region,” the slew rate of a tangent line to the
actual signal from the DC level to VREF(DC) level is used for the derating value (see Figure 33
on page 60).
4. Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid input
signal is still required to complete the transition and reach VIH(AC)/VIL(AC).
5. For slew rates between the values listed in this table, the derating values may be obtained
by linear interpolation.
6. These values are typically not subject to production test. They are verified by design and
characterization.
7. Single-ended DQS requires special derating. The values in Table 32 on page 57 are the DQS
single-ended slew rate derating with DQS referenced at VREF and DQ referenced at the logic
levels tDSb and tDHb. Converting the derated base values from DQs referenced to the AC/DC
trip points to DQs referenced to VREF is listed in Table 34 on page 58 and Table 35 on
page 58. Table 34 on page 58 provides the VREF-based fully derated values for the DQ (tDSa
and tDHa) for DDR2-533. Table 35 on page 58 provides the VREF-based fully derated values
for the DQ (tDSa and tDHa) for DDR2-400.
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©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
DDR2-667/DDR2-800/DDR2-1066 tDS, tDH Derating Values with Differential Strobe
Table 31:
All units are shown in picoseconds
DQS, DQS# Differential Slew Rate
DQ
Slew
Rate
(V/ns)
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
2.8 V/ns
Δ
DS
t
Δ
DH
t
2.4 V/ns
Δ
DS
t
Δ
DH
t
2.0 V/ns
Δ
DS
t
Δ
DH
t
100
63
100
63
100
63
67
42
67
42
67
42
0
0
0
0
0
0
–5
–14
–5
–14
–5
–14
–13 –31 –13 –31 –13 –31
–22 –54 –22 –54 –22 –54
–34 –83 –34 –83 –34 –83
–60 –125 –60 –125 –60 –125
–100 –188 –100 –188 –100 –188
Notes:
1.8 V/ns
t
Δ
DS
112
79
12
7
–1
–10
–22
–48
–88
Δ
DH
1.6 V/ns
Δ
DS
t
t
75
54
12
–2
–19
–42
–71
–113
–176
124
91
24
19
11
2
–10
–36
–76
t
Δ
DH
87
66
24
10
–7
–30
–59
–101
–164
1.4 V/ns
Δ
DS
Δ
DH
t
t
136
103
36
31
23
14
2
–24
–64
99
78
36
22
5
–18
–47
–89
–152
1.2 V/ns
Δ
DS
Δ
DH
1.0 V/ns
Δ
DS
Δ
DH
0.8 V/ns
Δ
DS
Δ
DH
t
t
t
t
t
t
148
115
48
43
35
26
14
–12
–52
111
90
48
34
17
–6
–35
–77
–140
160
127
60
55
47
38
26
0
–40
123
102
60
46
29
6
–23
–65
–128
172
139
72
67
59
50
38
12
–28
135
114
72
58
41
18
–11
–53
–116
1. For all input signals the total tDS and tDH required is calculated by adding the data sheet
value to the derating value listed in Table 31.
2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last crossing
of VREF(DC) and the first crossing of VIH(AC) MIN. tDS nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VREF(DC) and the first crossing of
VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between
the shaded “VREF(DC) to AC region,” use the nominal slew rate for the derating value (see
Figure 30 on page 59). If the actual signal is later than the nominal slew rate line anywhere
between shaded “VREF(DC) to AC region,” the slew rate of a tangent line to the actual signal
from the AC level to DC level is used for the derating value (see Figure 31 on page 59).
3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF(DC). tDH nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing
of VREF(DC). If the actual signal is always later than the nominal slew rate line between the
shaded “DC level to VREF(DC) region,” use the nominal slew rate for the derating value (see
Figure 32 on page 60). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded “DC to VREF(DC) region,” the slew rate of a tangent line to the
actual signal from the DC level to VREF(DC) level is used for the derating value (see Figure 33
on page 60).
4. Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid input
signal is still required to complete the transition and reach VIH(AC)/VIL(AC).
5. For slew rates between the values listed in this table, the derating values may be obtained
by linear interpolation.
6. These values are typically not subject to production test. They are verified by design and
characterization.
7. Single-ended DQS requires special derating. The values in Table 32 on page 57 are the DQS
single-ended slew rate derating with DQS referenced at VREF and DQ referenced at the logic
levels tDSb and tDHb. Converting the derated base values from DQs referenced to the AC/DC
trip points to DQs referenced to VREF is listed in Table 33 on page 57. Table 33 on page 57
provides the VREF-based fully derated values for the DQ (tDSa and tDHa) for DDR2-667. It is
not advised to operate DDR2-800 and DDR2-1066 devices with single-ended DQS; however
Table 32 on page 57 would be used with the base values.
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512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Table 32:
Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb
Reference points indicated in bold; Derating values are to be used with base tDSb- and tDHb-specified values
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns
DQ
(V/ns) tDS tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
130 53
97
32
30 –10
25 –24
17 –41
5
–64
–7 –93
–28 –135
–78 –198
Table 33:
1.8 V/ns
t
t
130
97
30
25
17
5
–7
–28
–78
53
32
–10
–24
–41
–64
–93
–135
–198
DS
DH
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
t
t
t
t
t
t
t
t
130
97
30
25
17
5
–7
–28
–78
53
32
–10
–24
–41
–64
–93
–135
–198
130
97
30
25
17
5
–7
–28
–78
53
32
–10
–24
–41
–64
–93
–135
–198
130
97
30
25
17
5
–7
–28
–78
53
32
–10
–24
–41
–64
–93
–135
–198
145
112
45
40
32
20
8
–13
–63
48
27
–15
–29
–46
–69
–98
–140
–203
DS
DH
DS
DH
DS
DH
DS
DH
0.8 V/ns
0.6 V/ns
0.4V/ns
t
t
t
t
t
t
155
122
55
50
42
30
18
–3
–53
45
24
–18
–32
–49
–72
–102
–143
–206
165
132
65
60
52
40
28
7
–43
41
20
–22
–36
–53
–75
–105
–147
–210
175
142
75
70
61
50
38
17
–33
38
17
–25
–39
–56
–79
–108
–150
–213
DS
DH
DS
DH
DS
DH
Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667
Reference points indicated in bold
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns
DQ
t
(V/ns) DS tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
330
330
330
347
367
391
426
472
522
291
290
290
290
290
290
290
290
289
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
0.8 V/ns
0.6 V/ns
0.4V/ns
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
330
330
330
347
367
391
426
472
522
291
290
290
290
290
290
290
290
289
330
330
330
347
367
391
426
472
522
291
290
290
290
290
290
290
290
289
330
330
330
347
367
391
426
472
522
291
290
290
290
290
290
290
290
289
330
330
330
347
367
391
426
472
522
291
290
290
290
290
290
290
290
289
345
345
345
362
382
406
441
487
537
286
285
285
285
285
285
285
285
284
355
355
355
372
392
416
451
497
547
282
282
282
282
282
281
282
282
281
365
365
365
382
402
426
461
507
557
29
279
278
278
278
278
278
278
278
375
375
375
392
412
436
471
517
567
276
275
275
275
275
275
275
275
274
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Input Slew Rate Derating
Table 34:
Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533
Reference points indicated in bold
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns
DQ
(V/ns) tDS tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
355
364
380
402
429
463
510
572
647
Table 35:
341
340
340
340
340
340
340
340
339
1.8 V/ns
1.6 V/ns
t
t
t
355
364
380
402
429
463
510
572
647
341
340
340
340
340
340
340
340
339
355
364
380
402
429
463
510
572
647
DS
DH
DS
1.4 V/ns
1.2 V/ns
1.0 V/ns
t
t
t
t
t
341
340
340
340
340
340
340
340
339
355
364
380
402
429
463
510
572
647
341
340
340
340
340
340
340
340
339
355
364
380
402
429
463
510
572
647
341
340
340
340
340
340
340
340
339
DH
DS
DH
DS
DH
0.8 V/ns
t
t
t
370
379
395
417
444
478
525
587
662
336
335
335
335
335
335
335
335
334
380
389
405
427
454
488
535
597
672
DS
DH
DS
0.6 V/ns
0.4V/ns
t
t
t
t
t
332
332
332
332
332
331
332
332
331
390
399
415
437
464
498
545
607
682
329
329
328
328
328
328
328
328
328
400
409
425
447
474
508
555
617
692
326
325
325
325
325
325
325
325
324
DH
DS
DH
DS
DH
Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400
Reference points indicated in bold
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns
DQ
t
(V/ns) DS tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
405
414
430
452
479
513
560
622
697
391
390
390
390
390
390
390
390
389
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
0.8 V/ns
0.6 V/ns
0.4V/ns
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
405
414
430
452
479
513
560
622
697
391
390
390
390
390
390
390
390
389
405
414
430
452
479
513
560
622
697
391
390
390
390
390
390
390
390
389
405
414
430
452
479
513
560
622
697
391
390
390
390
390
390
390
390
389
405
414
430
452
479
513
560
622
697
391
390
390
390
390
390
390
390
389
420
429
445
467
494
528
575
637
712
386
385
385
385
385
385
385
385
384
430
439
455
477
504
538
585
647
722
382
382
382
382
382
381
382
382
381
440
449
465
487
514
548
595
657
732
379
379
378
378
378
378
378
378
378
450
459
475
497
524
558
605
667
742
376
375
375
375
375
375
375
375
374
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Input Slew Rate Derating
Figure 30:
Nominal Slew Rate for tDS
DQS1
DQS#1
tDS
tDH
tDS
tDH
VDDQ
VIH(AC) MIN
VREF to AC
region
VIH(DC) MIN
Nominal
slew rate
VREF(DC)
Nominal
slew rate
VIL(DC) MAX
VREF to AC
region
VIL(AC) MAX
VSS
ΔTR
ΔTF
VREF(DC) - VIL(AC) MAX
Setup slew rate
=
falling signal
ΔTF
Notes:
Figure 31:
VIH(AC) MIN - VREF(DC)
Setup slew rate
=
rising signal
ΔTR
1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.
Tangent Line for tDS
DQS1
DQS#1
t
DS
VDDQ
t
t
DH
DS
t
DH
VIH(AC) MIN
Nominal
line
VREF to AC
region
VIH(DC) MIN
Tangent line
VREF(DC)
Tangent line
VIL(DC) MAX
Nominal line
VREF to AC
region
VIL(AC) MAX
ΔTR
ΔTF
VSS
Tangent line (VREF[DC] - VIL[AC] MAX)
Setup slew rate
=
falling signal
ΔTF
Notes:
Tangent line (VIH[AC] MIN - VREF[DC])
Setup slew rate
=
rising signal
ΔTR
1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.
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Input Slew Rate Derating
Figure 32:
Nominal Slew Rate for tDH
DQS1
DQS#1
tIS
tIS
tIH
tIH
VDDQ
VIH(AC) MIN
VIH(DC) MIN
DC to VREF
region
Nominal
slew rate
VREF(DC)
Nominal
slew rate
DC to VREF
region
VIL(DC) MAX
VIL(AC) MAX
VSS
ΔTF
ΔTR
Hold slew rate VREF(DC) - VIL(DC) MAX
=
rising signal
ΔTR
Notes:
Figure 33:
Hold slew rate VIH(DC) MIN - VREF(DC)
=
falling signal
ΔTF
1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.
Tangent Line for tDH
DQS1
DQS#1
tIS
tIS
tIH
tIH
VDDQ
VIH(AC) MIN
Nominal
line
VIH(DC) MIN
DC to VREF
region
Tangent
line
VREF(DC)
Tangent
line
Nominal
line
DC to VREF
region
VIL(DC) MAX
VIL(AC) MAX
VSS
ΔTF
ΔTR
Hold slew rate Tangent line (VREF[DC] - VIL[DC] MAX) Hold slew rate Tangent line (VIH[DC] MIN - VREF[DC])
=
=
rising signal
falling signal
ΔTR
ΔTF
Notes:
1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.
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Input Slew Rate Derating
Figure 34:
AC Input Test Signal Waveform Command/Address Balls
CK#
CK
tIS
b
Logic levels
tIS
b
tIH
b
tIH
b
VDDQ
VSWING (MAX)
VIH(AC) MIN
VIH(DC) MIN
VREF(DC)
VIL(DC) MIN
VIL(AC) MIN
tIS
a
VREF levels
Figure 35:
tIH
a
tIS
a
tIH
a
VSSQ
AC Input Test Signal Waveform for Data with DQS, DQS# (Differential)
DQS#
DQS
tDS
b
tDH
b
tDS
b
tDH
b
Logic levels
VDDQ
VSWING (MAX)
VIH(AC) MIN
VIH(DC) MIN
VREF(DC)
VIL(DC) MAX
VIL(AC) MAX
VSSQ
VREF levels
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DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
tDS
a
61
tDH
a
tDS
a
tDH
a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 36:
AC Input Test Signal Waveform for Data with DQS (Single-Ended)
VREF
DQS
tDS
b
Logic levels
tDH
b
tDS
b
tDH
b
VDDQ
VIH(AC) MIN
VSWING (MAX)
VIH(DC) MIN
VREF(DC)
VIL(DC) MAX
VIL(AC) MAX
tDS
a
VREF levels
Figure 37:
tDH
a
tDS
a
tDH
a
VSSQ
AC Input Test Signal Waveform (Differential)
VDDQ
VTR
Crossing point
VSWING
VIX
VCP
VSSQ
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512Mb: x4, x8, x16 DDR2 SDRAM
Commands
Commands
Truth Tables
The following tables provide a quick reference of available DDR2 SDRAM commands,
including CKE power-down modes and bank-to-bank commands.
Table 36:
Truth Table – DDR2 Commands
Notes: 1–3 apply to the entire table
CKE
Previous Current
Cycle
Cycle
Function
LOAD MODE
REFRESH
SELF REFRESH entry
SELF REFRESH exit
H
H
H
L
H
H
L
H
Single bank PRECHARGE
All banks PRECHARGE
Bank activate
WRITE
H
H
H
H
WRITE with auto
precharge
READ
CS#
RAS# CAS# WE#
BA2–
BA0
L
L
L
X
H
L
L
L
H
L
L
L
X
H
H
H
H
L
L
H
H
X
H
L
L
H
L
BA
X
X
X
H
H
H
H
L
L
L
H
L
L
L
L
L
H
H
L
H
L
L
BA
H
H
L
H
L
H
BA
BA
X
BA
BA
READ with auto
precharge
NO OPERATION
Device DESELECT
Power-down entry
H
H
L
H
L
H
BA
H
H
H
X
X
L
L
H
H
X
X
H
X
H
H
X
X
H
X
H
H
X
X
H
X
H
X
X
X
Power-down exit
L
H
H
L
H
L
Notes:
X
An–A11
X
X
X
A10
OP code
X
X
X
A9–A0
4, 6
X
X
X
X
X
L
X
H
X
Row address
Column
L
Column
address
address
Column
H
Column
address
address
Column
L
Column
address
address
Column
H
Column
address
address
X
X
X
X
X
X
X
X
X
X
X
Notes
X
4, 7
6
4
4, 5, 6, 8
4, 5, 6, 8
4, 5, 6, 8
4, 5, 6, 8
9
9
1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the
rising edge of the clock.
2. The state of ODT does not affect the states described in this table. The ODT function is not
available during self refresh. See “ODT Timing” on page 117 for details.
3. “X” means “H or L” (but a defined logic level) for valid IDD measurements.
4. BA2 is only applicable for densities >1Gb.
5. An is the most significant address bit for a given density and configuration. Some larger
address bits may be “Don’t Care” during column addressing, depending on density and configuration.
6. Bank addresses (BA) determine which bank is to be operated upon. BA during a LOAD
MODE command selects which mode register is programmed.
7. SELF REFRESH exit is asynchronous.
8. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See Figure 51 on
page 87 and Figure 63 on page 98 for other restrictions and details.
9. The power-down mode does not perform any REFRESH operations. The duration of powerdown is limited by the refresh requirements outlined in the AC parametric section.
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Commands
Table 37:
Truth Table – Current State Bank n – Command to Bank n
Notes: 1–6 apply to the entire table
Current
State
CS#
RAS#
CAS#
WE#
Command/Action
Notes
Any
H
L
X
H
X
H
X
H
Idle
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
H
L
H
H
L
H
L
L
L
L
H
L
L
H
L
L
H
H
H
L
H
L
L
H
L
L
H
L
L
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous
operation)
ACTIVATE (select and activate row)
REFRESH
LOAD MODE
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (start PRECHARGE)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (start PRECHARGE)
7
7
8
8
9
8
8, 10
8
8
8
9
Row active
Read (autoprecharge
disabled)
Write (autoprecharge
disabled)
Notes:
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been met
(if the previous state was self refresh).
2. This table is bank-specific, except where noted (the current state is for a specific bank and
the commands shown are those allowed to be issued to that bank when in that state).
Exceptions are covered in the notes below.
3. Current state definitions:
The bank has been precharged, tRP has been met, and any READ burst
is complete.
Row active:
A row in the bank has been activated, and tRCD has been met. No
data bursts/accesses and no register accesses are in progress.
Read:
A READ burst has been initiated, with auto precharge disabled and
has not yet terminated.
Write:
A WRITE burst has been initiated with auto precharge disabled and
has not yet terminated.
4. The following states must not be interrupted by a command issued to the same bank. Issue
DESELECT or NOP commands, or allowable commands to the other bank, on any clock edge
occurring during these states. Allowable commands to the other bank are determined by its
current state and this table, and according to Table 38 on page 66.
Idle:
Precharge:
Read with auto
precharge
enabled:
Row activate:
Write with auto
precharge
enabled:
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Starts with registration of a PRECHARGE command and ends when tRP
is met. After tRP is met, the bank will be in the idle state.
Starts with registration of a READ command with auto precharge
enabled and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
Starts with registration of an ACTIVATE command and ends when
t
RCD is met. After tRCD is met, the bank will be in the row active state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
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Commands
5. The following states must not be interrupted by any executable command (DESELECT or
NOP commands must be applied on each positive clock edge during these states):
Starts with registration of a REFRESH command and ends when tRFC is
met. After tRFC is met, the DDR2 SDRAM will be in the all banks idle
state.
Accessing mode Starts with registration of the LOAD MODE command and ends when
t
MRD has been met. After tMRD is met, the DDR2 SDRAM will be in
register:
the all banks idle state.
Precharge all:
Starts with registration of a PRECHARGE ALL command and ends
when tRP is met. After tRP is met, all banks will be in the idle state.
All states and sequences not shown are illegal or reserved.
Not bank-specific; requires that all banks are idle and bursts are not in progress.
READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
precharge enabled and READs or WRITEs with auto precharge disabled.
May or may not be bank-specific; if multiple banks are to be precharged, each must be in a
valid state for precharging.
A WRITE command may be applied after the completion of the READ burst.
Refresh:
6.
7.
8.
9.
10.
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Commands
Table 38:
Truth Table – Current State Bank n – Command to Bank m
Notes: 1–6 apply to the entire table
Current State
Any
Idle
Row active, active,
or precharge
Read (auto
precharge
disabled)
Write (auto
precharge
disabled)
Read (with autoprecharge)
Write (with autoprecharge)
CS#
RAS#
CAS#
WE#
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
X
H
X
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
X
H
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
Notes:
Command/Action
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to bank m
ACTIVATE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVATE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVATE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVATE (select and activate row)
READ (select column and start new READ burst
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVATE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
Notes
7
7
7
7, 8
7, 9, 10
7
7
7, 8
7, 10
7
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been met
(if the previous state was self refresh).
2. This table describes an alternate bank operation, except where noted (the current state is
for bank n and the commands shown are those allowed to be issued to bank m, assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
3. Current state definitions:
The bank has been precharged, tRP has been met, and any READ burst is
complete.
Row active: A row in the bank has been activated and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read:
A READ burst has been initiated with auto precharge disabled and has not
yet terminated.
Write:
A WRITE burst has been initiated with auto precharge disabled and has not
yet terminated.
Idle:
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Commands
READ with
auto
precharge
enabled/
WRITE with
auto
precharge
enabled:
The READ with auto precharge enabled or WRITE with auto precharge
enabled states can each be broken into two parts: the access period and the
precharge period. For READ with auto precharge, the precharge period is
defined as if the same burst was executed with auto precharge disabled and
then followed with the earliest possible PRECHARGE command that still
accesses all of the data in the burst. For WRITE with auto precharge, the
precharge period begins when tWR ends, with tWR measured as if auto
precharge was disabled. The access period starts with registration of the
command and ends where the precharge period (or tRP) begins. This device
supports concurrent auto precharge such that when a READ with auto
precharge is enabled or a WRITE with auto precharge is enabled, any
command to other banks is allowed, as long as that command does not
interrupt the read or write data transfer already in process. In either case, all
other related limitations apply (contention between read data and write
data must be avoided).
The minimum delay from a READ or WRITE command with auto precharge enabled to a
command to a different bank is summarized in Table 39:
Table 39:
Minimum Delay with Auto Precharge Enabled
From Command
(Bank n)
WRITE with auto
precharge
READ with auto
precharge
To Command (Bank m)
READ or READ with auto
precharge
WRITE or WRITE with auto
precharge
PRECHARGE or ACTIVATE
READ or READ with auto
precharge
WRITE or WRITE with auto
precharge
PRECHARGE or ACTIVATE
Minimum Delay
(with Concurrent
Auto Precharge)
(CL - 1) + (BL/2) +
tWTR
Units
tCK
(BL/2)
tCK
1
(BL/2)
tCK
(BL/2) + 2
tCK
1
tCK
tCK
4.
5.
6.
7.
REFRESH and LOAD MODE commands may only be issued when all banks are idle.
Not used.
All states and sequences not shown are illegal or reserved.
READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
precharge enabled and READs or WRITEs with auto precharge disabled.
8. A WRITE command may be applied after the completion of the READ burst.
9. Requires appropriate DM.
10. The number of clock cycles required to meet tWTR is either two or tWTR/tCK, whichever is
greater.
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in
progress are not affected. DESELECT is also referred to as COMMAND INHIBIT.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to
perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted
commands from being registered during idle or wait states. Operations already in
progress are not affected.
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Commands
LOAD MODE (LM)
The mode registers are loaded via bank address and address inputs. The bank address
balls determine which mode register will be programmed. See “Mode Register (MR)” on
page 73. The LM command can only be issued when all banks are idle, and a subsequent
executable command cannot be issued until tMRD is met.
ACTIVATE
The ACTIVATE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the bank address inputs determines the bank, and the
address inputs select the row. This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A PRECHARGE command must be issued
before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on
the bank address inputs determine the bank, and the address provided on address
inputs A0–Ai (where Ai is the most significant column address bit for a given configuration) selects the starting column location. The value on input A10 determines whether
or not auto precharge is used. If auto precharge is selected, the row being accessed will
be precharged at the end of the READ burst; if auto precharge is not selected, the row will
remain open for subsequent accesses.
DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to
be issued prior to tRCD (MIN) by delaying the actual registration of the READ/WRITE
command to the internal device by AL clock cycles.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the bank select inputs selects the bank, and the address provided on inputs A0–Ai
(where Ai is the most significant column address bit for a given configuration) selects the
starting column location. The value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the WRITE burst; if auto precharge is not selected, the row will
remain open for subsequent accesses.
DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to
be issued prior to tRCD (MIN) by delaying the actual registration of the READ/WRITE
command to the internal device by AL clock cycles.
Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW, the
corresponding data will be written to memory; if the DM signal is registered HIGH, the
corresponding data inputs will be ignored, and a WRITE will not be executed to that
byte/column location (see Figure 68 on page 103).
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row activation a
specified time (tRP) after the PRECHARGE command is issued, except in the case of
concurrent auto precharge, where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer in the current bank and does
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Commands
not violate any other timing parameters. After a bank has been precharged, it is in the
idle state and must be activated prior to any READ or WRITE commands being issued to
that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle
state) or if the previously open row is already in the process of precharging. However, the
precharge period will be determined by the last PRECHARGE command issued to the
bank.
REFRESH
REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to
CAS#-before-RAS# (CBR) REFRESH. All banks must be in the idle mode prior to issuing a
REFRESH command. This command is nonpersistent, so it must be issued each time a
refresh is required. The addressing is generated by the internal refresh controller. This
makes the address bits a “Don’t Care” during a REFRESH command.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if
the rest of the system is powered down. When in the self refresh mode, the DDR2
SDRAM retains data without external clocking. All power supply inputs (including VREF )
must be maintained at valid levels upon entry/exit and during SELF REFRESH operation.
The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW.
The DLL is automatically disabled upon entering self refresh and is automatically
enabled upon exiting self refresh.
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Operations
Operations
Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. Figure 38 illustrates and the notes outline the sequence of progression required for power-up and
initialization.
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Figure 38: DDR2 Power-Up and Initialization
VDD
VDDL
VDDQ
tVTD1
VTT1
VREF
T0
tCK
Ta0
Tb0
Tc0
Td0
Te0
Tf0
Tg0
Th0
Ti0
Tj0
Tk0
Tl0
Tm0
NOP3
PRE
LM5
LM6
LM7
LM8
PRE9
REF10
REF10
LM11
LM12
LM13
Valid14
A10 = 1
Code
Code
Code
Code
A10 = 1
Code
Code
Code
Valid
CK#
CK
tCL
LVCMOS
CKE low level2
tCL
SSTL_18 2
low level
ODT
Command
DM
Address
15
16
71
15
DQS
High-Z
15
High-Z
RTT
High-Z
DQ
Power-up:
VDD and stable
clock (CK, CK#)
T = 400ns (MIN)4
tRPA
tMRD
tMRD
EMR(2)
EMR(3)
tMRD
tMRD
tRPA
tRFC
tRFC
tMRD
tMRD
tMRD
See note 10
EMR
MR without
DLL RESET
EMR with
OCD default
EMR with
OCD exit
200 cycles of CK are required before a READ command can be issued
Normal
operation
MR with
DLL RESET
Indicates A Break in
Time Scale
Notes:
Don’t care
1. Applying power; if CKE is maintained below 0.2 × VDDQ, outputs remain disabled. To guarantee RTT (ODT resistance) is off,
VREF must be valid and a low level must be applied to the ODT ball (all other inputs may be undefined; I/Os and outputs
must be less than VDDQ during voltage ramp time to avoid DDR2 SDRAM device latch-up). VTT is not applied directly to
the device; however, tVTD should be ≥0 to avoid device latch-up. At least one of the following two sets of conditions (A
or B) must be met to obtain a stable supply state (stable supply defined as VDD, VDDL, VDDQ, VREF, and VTT are between
their minimum and maximum values as stated in Table 12 on page 38):
512Mb: x4, x8, x16 DDR2 SDRAM
Operations
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T = 200µs (MIN)3
512Mb: x4, x8, x16 DDR2 SDRAM
Operations
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
A. Single power source: The VDD voltage ramp from 300mV to VDD (MIN) must take no
longer than 200ms; during the VDD voltage ramp, |VDD - VDDQ| ≤ 0.3V. Once supply voltage ramping is complete (when VDDQ crosses VDD [MIN]), Table 12 on page 38 specifications apply.
• VDD, VDDL, and VDDQ are driven from a single power converter output
• VTT is limited to 0.95V MAX
• VREF tracks VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during supply ramp time
• VDDQ ≥ VREF at all times
B. Multiple power sources: VDD ≥ VDDL ≥ VDDQ must be maintained during supply voltage
ramping, for both AC and DC levels, until supply voltage ramping completes (VDDQ
crosses VDD [MIN]). Once supply voltage ramping is complete, Table 12 on page 38 specifications apply.
• Apply VDD and VDDL before or at the same time as VDDQ; VDD/VDDL voltage ramp
time must be ≤200ms from when VDD ramps from 300mV to VDD (MIN)
• Apply VDDQ before or at the same time as VTT; the VDDQ voltage ramp time from
when VDD (MIN) is achieved to when VDDQ (MIN) is achieved must be ≤500ms; while
VDD is ramping, current can be supplied from VDD through the device to VDDQ
• VREF must track VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during
supply ramp time; VDDQ ≥ VREF must be met at all times
• Apply VTT; the VTT voltage ramp time from when VDDQ (MIN) is achieved to when
VTT (MIN) is achieved must be no greater than 500ms
CKE requires LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device
power-up prior to VREF being stable. After state T0, CKE is required to have SSTL_18 input
levels. Once CKE transitions to a high level, it must stay HIGH for the duration of the initialization sequence.
For a minimum of 200µs after stable power and clock (CK, CK#), apply NOP or DESELECT
commands, then take CKE HIGH.
Wait a minimum of 400ns then issue a PRECHARGE ALL command.
Issue a LOAD MODE command to the EMR(2). To issue an EMR(2) command, provide LOW to
BA0, and provide HIGH to BA1; set register E7 to “0” or “1” to select appropriate self
refresh rate; remaining EMR(2) bits must be “0” (see "Extended Mode Register 2 (EMR2)"
on page 81 for all EMR(2) requirements).
Issue a LOAD MODE command to the EMR(3). To issue an EMR(3) command, provide HIGH
to BA0 and BA1; remaining EMR(3) bits must be “0.” See “Extended Mode Register 3 (EMR
3)” on page 82 for all EMR(3) requirements.
Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE command,
provide LOW to BA1 and A0; provide HIGH to BA0; bits E7, E8, and E9 can be set to “0” or
“1;” Micron recommends setting them to “0;” remaining EMR bits must be “0.” See
“Extended Mode Register (EMR)” on page 77 for all EMR requirements.
Issue a LOAD MODE command to the MR for DLL RESET. 200 cycles of clock input is required
to lock the DLL. To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA1 and BA0;
CKE must be HIGH the entire time the DLL is resetting; remaining MR bits must be “0.” See
“Mode Register (MR)” on page 73 for all MR requirements.
Issue PRECHARGE ALL command.
Issue two or more REFRESH commands.
Issue a LOAD MODE command to the MR with LOW to A8 to initialize device operation
(that is, to program operating parameters without resetting the DLL). To access the MR, set
BA0 and BA1 LOW; remaining MR bits must be set to desired settings. See “Mode Register
(MR)” on page 73 for all MR requirements.
Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and
E9 to “1,” and then setting all other desired parameters. To access the EMR, set BA0 LOW
and BA1 HIGH (see "Extended Mode Register (EMR)" on page 77 for all EMR requirements.
Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9
to “0,” and then setting all other desired parameters. To access the extended mode registers, EMR, set BA0 LOW and BA1 HIGH for all EMR requirements.
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Operations
14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after
the DLL RESET at Tf0.
15. DM represents DM for the x4, x8 configurations and UDM, LDM for the x16 configuration;
DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the appropriate
configuration (x4, x8, x16); DQ represents DQ0–DQ3 for x4, DQ–DQ7 for x8 and DQ0–DQ15
for x16.
16. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are
required to be decoded).
Mode Register (MR)
The mode register is used to define the specific mode of operation of the DDR2 SDRAM.
This definition includes the selection of a burst length, burst type, CAS latency, operating mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 39
on page 74. Contents of the mode register can be altered by reexecuting the LOAD
MODE (LM) command. If the user chooses to modify only a subset of the MR variables,
all variables must be programmed when the command is issued.
The MR is programmed via the LM command and will retain the stored information
until it is programmed again or until the device loses power (except for bit M8, which is
self-clearing). Reprogramming the mode register will not alter the contents of the
memory array, provided it is performed correctly.
The LM command can only be issued (or reissued) when all banks are in the precharged
state (idle state) and no bursts are in progress. The controller must wait the specified
time tMRD before initiating any subsequent operations such as an ACTIVATE command.
Violating either of these requirements will result in an unspecified operation.
Burst Length
Burst length is defined by bits M0–M2, as shown in Figure 39 on page 74. Read and write
accesses to the DDR2 SDRAM are burst-oriented, with the burst length being programmable to either four or eight. The burst length determines the maximum number of
column locations that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most
significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The
programmed burst length applies to both READ and WRITE bursts.
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Operations
Figure 39:
Mode Register (MR) Definition
1
2
BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
16 15 14 n 12 11 10
0
MR
WR
0 PD
Mode Register (Mx)
9
8 7 6 5 4 3 2 1 0
DLL TM CAS# Latency BT Burst Length
M12 PD Mode
0
Fast exit
(normal)
1
Slow exit
(low power)
M11 M10 M9
0 Normal
0
0
0
Reserved
1
0
0
1
Reserved
0
1
0
4
0
1
1
8
Test
M8 DLL Reset
0
No
1
0
0
Reserved
1
Yes
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Write Recovery
0
0
0
Reserved
0
0
1
2
M3
0
1
0
3
0
Sequential
0
1
1
4
1
Interleaved
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
M15 M14
Notes:
M2 M1 M0 Burst Length
M7 Mode
M6 M5 M4
Mode Register Definition
0
0
Mode register (MR)
0
1
Extended mode register (EMR)
1
0
Extended mode register (EMR2)
1
1
Extended mode register (EMR3)
Burst Type
CAS Latency (CL)
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
1. M16 (BA2) is only applicable for densities >1Gb, reserved for future use, and must be programmed to “0.”
2. Mode bits (Mn) with corresponding address balls (An) greater than M12 (A12) are reserved
for future use and must be programmed to “0.”
3. Not all listed WR and CL options are supported in any individual speed grade.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved.
The burst type is selected via bit M3, as shown in Figure 39. The ordering of accesses
within a burst is determined by the burst length, the burst type, and the starting column
address, as shown in Table 40 on page 75. DDR2 SDRAM supports 4-bit burst mode and
8-bit burst mode only. For 8-bit burst mode, full interleaved address ordering is
supported; however, sequential address ordering is nibble-based.
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Operations
Table 40:
Burst Definition
Burst Length
4
8
Starting Column
Address
(A2, A1, A0)
Order of Accesses Within a Burst
Burst Type = Sequential
Burst Type = Interleaved
00
01
10
11
000
001
010
011
100
101
110
111
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Operating Mode
The normal operating mode is selected by issuing a command with bit M7 set to “0,” and
all other bits set to the desired values, as shown in Figure 39 on page 74. When bit M7 is
“1,” no other bits of the mode register are programmed. Programming bit M7 to “1”
places the DDR2 SDRAM into a test mode that is only used by the manufacturer and
should not be used. No operation or functionality is guaranteed if M7 bit is “1.”
DLL RESET
DLL RESET is defined by bit M8, as shown in Figure 39 on page 74. Programming bit M8
to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns
back to a value of “0” after the DLL RESET function has been issued.
Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ
command can be issued to allow time for the internal clock to be synchronized with the
external clock. Failing to wait for synchronization to occur may result in a violation of
the tAC or tDQSCK parameters.
Write Recovery
Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 39 on page 74.
The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation. During WRITE with auto precharge operation, the DDR2 SDRAM delays the
internal auto precharge operation by WR clocks (programmed in bits M9–M11) from the
last data burst. An example of WRITE with auto precharge is shown in Figure 67 on
page 102.
WR values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits M9–M11. The
user is required to program the value of WR, which is calculated by dividing tWR (in
nanoseconds) by tCK (in nanoseconds) and rounding up a noninteger value to the next
integer; WR (cycles) = tWR (ns)/tCK (ns). Reserved states should not be used as an
unknown operation or incompatibility with future versions may result.
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Operations
Power-Down Mode
Active power-down (PD) mode is defined by bit M12, as shown in Figure 39 on page 74.
PD mode allows the user to determine the active power-down mode, which determines
performance versus power savings. PD mode bit M12 does not apply to precharge PD
mode.
When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.
The tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is
enabled. The tXARDS parameter is used for slow-exit active PD exit timing. The DLL can
be enabled but “frozen” during active PD mode because the exit-to-READ command
timing is relaxed. The power difference expected between IDD3P normal and IDD3P lowpower mode is defined in Table 11 on page 28.
CAS Latency (CL)
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 39 on page 74. CL is
the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending
on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be
used as an unknown operation otherwise incompatibility with future versions may
result.
DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This
feature allows the READ command to be issued prior to tRCD (MIN) by delaying the
internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in
further detail in “Posted CAS Additive Latency (AL)” on page 80.
Examples of CL = 3 and CL = 4 are shown in Figure 40 on page 77; both assume AL = 0. If
a READ command is registered at clock edge n, and the CL is m clocks, the data will be
available nominally coincident with clock edge n + m (this assumes AL = 0).
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Operations
Figure 40:
CAS Latency (CL)
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
DQS, DQS#
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
CL = 3 (AL = 0)
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
DQS, DQS#
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
CL = 4 (AL = 0)
Transitioning data
Notes:
Don’t care
1. BL = 4.
2. Posted CAS# additive latency (AL) = 0.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
Extended Mode Register (EMR)
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable, output drive strength, ondie termination (ODT), posted AL, off-chip driver impedance calibration (OCD), DQS#
enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These functions are controlled via the bits shown in Figure 41 on page 78. The EMR is programmed
via the LM command and will retain the stored information until it is programmed again
or the device loses power. Reprogramming the EMR will not alter the contents of the
memory array, provided it is performed correctly.
The EMR must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in an unspecified operation.
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Operations
Figure 41:
Extended Mode Register Definition
1
2
BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
16
0
1 0
15 14 n 12 11 10 9 8 7 6 5 4 3 2
MRS 0 Out RDQS DQS# OCD Program RTT Posted CAS# RTT ODS DLL
Address bus
Extended mode
register (Ex)
E0
DLL Enable
0
Enable (normal)
1
Disable (test/debug)
E12
Outputs
0
Enabled
E6 E2 RTT (Nominal)
1
Disabled
0 0
RTT disabled
0 1
75Ω
1 0
150Ω
E1
1 1
50Ω
0
Full
1
Reduced
E11 RDQS Enable
0
No
1
Yes
E10 DQS# Enable
Output Drive Strength
E5 E4 E3 Posted CAS# Additive Latency (AL)
0
Enable
0
0
0
0
1
Disable
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Reserved
E9 E8 E7 OCD Operation
0
0
0
OCD exit
0
0
1
Reserved
0
1
0
Reserved
1
0
0
Reserved
1
1
1
Enable OCD defaults
Mode Register Set
E15 E14
Notes:
A1 A0
0
0
0
1
Extended mode register (EMR)
1
0
Extended mode register (EMR2)
1
1
Extended mode register (EMR3)
Mode register (MR)
1. E16 (BA2) is only applicable for densities >1Gb, reserved for future use, and must be programmed to “0.”
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are reserved
for future use and must be programmed to “0.”
3. Not all listed AL options are supported in any individual speed grade.
4. As detailed on page 71, during initialization of the ODC operation, all three bits must be set
to “1” for the OCD default state, then set to “0” before initialization is finished.
DLL Enable/Disable
The DLL may be enabled or disabled by programming bit E0 during the LM command,
as shown in Figure 41. The DLL must be enabled for normal operation. DLL enable is
required during power-up initialization and upon returning to normal operation after
having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL
should always be followed by resetting the DLL using the LM command.
The DLL is automatically disabled when entering SELF REFRESH operation and is automatically reenabled and reset upon exit of SELF REFRESH operation.
Anytime the DLL is enabled (and subsequently reset), 200 clock cycles must occur before
a READ command can be issued to allow time for the internal clock to synchronize with
the external clock. Failing to wait for synchronization to occur may result in a violation
of the tAC or tDQSCK parameters.
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Operations
Anytime the DLL is disabled and the device is operated below 25MHz, any AUTOREFRESH command should be followed by a PRECHARGE ALL command.
Output Drive Strength
The output drive strength is defined by bit E1, as shown in Figure 41 on page 78. The
normal drive strength for all outputs is specified to be SSTL_18. Programming bit E1 = 0
selects normal (full strength) drive strength for all outputs. Selecting a reduced drive
strength option (E1 = 1) will reduce all outputs to approximately 45 to 60 percent of the
SSTL_18 drive strength. This option is intended for the support of lighter load and/or
point-to-point environments.
DQS# Enable/Disable
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the
differential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a
single-ended mode and the DQS# ball is disabled. When disabled, DQS# should be left
floating. This function is also used to enable/disable RDQS#. If RDQS is enabled
(E11 = 1) and DQS# is enabled (E10 = 0), then both DQS# and RDQS# will be enabled.
RDQS Enable/Disable
The RDQS ball is enabled by bit E11, as shown in Figure 41 on page 78. This feature is
only applicable to the x8 configuration. When enabled (E11 = 1), RDQS is identical in
function and timing to data strobe DQS during a READ. During a WRITE operation,
RDQS is ignored by the DDR2 SDRAM.
Output Enable/Disable
The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 41 on page 78.
When enabled (E12 = 0), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) function normally.
When disabled (E12 = 1), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) are disabled, thus
removing output buffer current. The output disable feature is intended to be used
during IDD characterization of read current.
On-Die Termination (ODT)
ODT effective resistance, RTT (EFF), is defined by bits E2 and E6 of the EMR, as shown in
Figure 41 on page 78. The ODT feature is designed to improve signal integrity of the
memory channel by allowing the DDR2 SDRAM controller to independently turn on/off
ODT for any or all devices. RTT effective resistance values of 50Ω, 75Ω, and 150Ω are
selectable and apply to each DQ, DQS/DQS#, RDQS/RDQS#, UDQS/UDQS#, LDQS/
LDQS#, DM, and UDM/LDM signals. Bits (E6, E2) determine what ODT resistance is
enabled by turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective resistance value is
selected by enabling switch “sw1,” which enables all R1 values that are 150Ω each,
enabling an effective resistance of 75Ω (RTT2 [EFF] = R2/2). Similarly, if “sw2” is enabled,
all R2 values that are 300Ω each, enable an effective ODT resistance of 150Ω
(RTT2 [EFF] = R2/2). Switch “sw3” enables R1 values of 100Ω, enabling effective resistance of 50Ω. Reserved states should not be used, as an unknown operation or incompatibility with future versions may result.
The ODT control ball is used to determine when RTT (EFF) is turned on and off,
assuming ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and
ODT input ball are only used during active, active power-down (both fast-exit and slowexit modes), and precharge power-down modes of operation.
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Operations
ODT must be turned off prior to entering self refresh mode. During power-up and initialization of the DDR2 SDRAM, ODT should be disabled until the EMR command is issued.
This will enable the ODT feature, at which point the ODT ball will determine the RTT
(EFF) value. Anytime the EMR enables the ODT function, ODT may not be driven HIGH
until eight clocks after the EMR has been enabled (see Figure 83 on page 118 for ODT
timing diagrams).
Off-Chip Driver (OCD) Impedance Calibration
The OFF-CHIP DRIVER function is an optional DDR2 JEDEC feature not supported by
Micron and thereby must be set to the default state. Enabling OCD beyond the default
settings will alter the I/O drive characteristics and the timing and output I/O specifications will no longer be valid (see "Initialization" on page 70 for proper setting of OCD
defaults).
Posted CAS Additive Latency (AL)
Posted CAS additive latency (AL) is supported to make the command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as
shown in Figure 41 on page 78. Bits E3–E5 allow the user to program the DDR2 SDRAM
with an AL of 0, 1, 2, 3, 4, 5, or 6 clocks. Reserved states should not be used as an
unknown operation or incompatibility with future versions may result.
In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued
prior to tRCD (MIN) with the requirement that AL ≤ tRCD (MIN). A typical application
using this feature would set AL = tRCD (MIN) - 1 × tCK. The READ or WRITE command is
held for the time of the AL before it is issued internally to the DDR2 SDRAM device. RL is
controlled by the sum of AL and CL; RL = AL + CL. Write latency (WL) is equal to RL
minus one clock; WL = AL + CL - 1 × tCK. An example of RL is shown in Figure 42 on
page 80. An example of a WL is shown in Figure 43 on page 81.
Figure 42:
CK#
READ Latency
T0
T1
T2
T3
T4
T5
T6
T7
T8
ACTIVE n
READ n
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
DQS, DQS#
tRCD (MIN)
DQ
AL = 2
CL = 3
DO
n
DO
n+1
DO
n+2
DO
n+3
RL = 5
Transitioning Data
Notes:
Don’t Care
1. BL = 4.
2. Shown with nominal tAC, tDQSCK, and tDQSQ.
3. RL = AL + CL = 5.
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Operations
Figure 43:
CK#
WRITE Latency
T0
T1
ACTIVE n
WRITE n
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
tRCD (MIN)
DQS, DQS#
AL = 2
CL - 1 = 2
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
WL = AL + CL - 1 = 4
Transitioning Data
Notes:
Don’t Care
1. BL = 4.
2. CL = 3.
3. WL = AL + CL - 1 = 4.
Extended Mode Register 2 (EMR2)
The extended mode register 2 (EMR2) controls functions beyond those controlled by the
mode register. Currently all bits in EMR2 are reserved, except for E7, which is used in
commercial or high-temperature operations, as shown in Figure 44. The EMR2 is
programmed via the LM command and will retain the stored information until it is
programmed again or until the device loses power. Reprogramming the EMR will not
alter the contents of the memory array, provided it is performed correctly.
Bit E7 (A7) must be programmed as “1” to provide a faster refresh rate on IT and AT
devices if TC exceeds 85°C.
EMR2 must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in an unspecified operation.
Figure 44:
Extended Mode Register 2 (EMR2) Definition
1
2
BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
16
0
10 9 8 7 6
0 0 0 SRT 0
5 4 3 2
0 0 0 0
1
0
0
0
Mode Register Set
E7
SRT Enable
Mode register (MR)
0
1X refresh rate (0°C to 85°C)
1
Extended mode register (EMR)
1
2X refresh rate (>85°C)
0
Extended mode register (EMR2)
1
Extended mode register (EMR3)
E15 E14
Notes:
15 14 n 12 11
MRS 0 0 0
0
0
0
1
1
Address bus
Extended mode
register (Ex)
1. E16 (BA2) is only applicable for densities >1Gb, reserved for future use, and must be programmed to “0.”
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are reserved
for future use and must be programmed to “0.”
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Operations
Extended Mode Register 3 (EMR 3)
The extended mode register 3 (EMR3) controls functions beyond those controlled by the
mode register. Currently all bits in EMR3 are reserved, as shown in Figure 45 on page 82.
The EMR3 is programmed via the LM command and will retain the stored information
until it is programmed again or until the device loses power. Reprogramming the EMR
will not alter the contents of the memory array, provided it is performed correctly.
EMR3 must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in an unspecified operation.
Figure 45:
Extended Mode Register 3 (EMR3) Definition
1
2
BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
16
15 14 n
12 11
10
0
MRS
0
0
E15 E14
Notes:
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Address bus
Extended mode
register (Ex)
Mode Register Set
0
0
0
1
Extended mode register (EMR)
1
0
Extended mode register (EMR2)
1
1
Extended mode register (EMR3)
Mode register (MR)
1. E16 (BA2) is only applicable for densities >1Gb, is reserved for future use, and must be programmed to “0.”
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are reserved
for future use and must be programmed to “0.”
ACTIVATE
Before any READ or WRITE commands can be issued to a bank within the DDR2
SDRAM, a row in that bank must be opened (activated), even when additive latency is
used. This is accomplished via the ACTIVATE command, which selects both the bank
and the row to be activated.
After a row is opened with an ACTIVATE command, a READ or WRITE command may be
issued to that row subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVATE command on which a READ or WRITE command can be
entered. The same procedure is used to convert other specification limits from time
units to clock cycles. For example, a tRCD (MIN) specification of 20ns with a 266 MHz
clock (tCK = 3.75ns) results in 5.3 clocks, rounded up to 6. This is shown in Figure 46 on
page 83, which covers any case where 5 < tRCD (MIN)/tCK ≤ 6. Figure 46 also shows the
case for tRRD where 2 < tRRD (MIN)/tCK ≤ 3.
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Operations
Figure 46:
Example: Meeting tRRD (MIN) and tRCD (MIN)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Command
ACT
NOP
NOP
ACT
NOP
NOP
NOP
NOP
NOP
RD/WR
Address
Row
CK#
CK
Bank address
Row
Bank x
Bank y
Row
Col
Bank z
Bank y
tRRD
tRRD
tRCD
Don’t Care
A subsequent ACTIVATE command to a different row in the same bank can only be
issued after the previous active row has been closed (precharged). The minimum time
interval between successive ACTIVATE commands to the same bank is defined by tRC.
A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVATE commands to different banks is defined by
t
RRD.
DDR2 devices with 8-banks (1Gb or larger) have an additional requirement: tFAW. This
requires no more than four ACTIVATE commands may be issued in any given tFAW
(MIN) period, as shown in Figure 47.
Figure 47:
Multi-Bank Activate Restriction
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Command
ACT
READ
ACT
READ
ACT
READ
ACT
READ
NOP
NOP
ACT
Address
Row
Col
Row
Col
Row
Col
Row
Col
Row
Bank a
Bank a
Bank b
Bank c
Bank c
Bank d
Bank d
Bank e
CK#
CK
Bank address
tRRD (MIN)
Bank b
tFAW (MIN)
Don’t Care
Notes:
1. DDR2-533 (-37E, x4 or x8), tCK = 3.75ns, BL = 4, AL = 3, CL = 4, tRRD (MIN) = 7.5ns,
tFAW (MIN) = 37.5ns.
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Operations
READ
READ bursts are initiated with a READ command. The starting column and bank
addresses are provided with the READ command, and auto precharge is either enabled
or disabled for that burst access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto precharge is disabled,
the row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the starting column address will
be available READ latency (RL) clocks later. RL is defined as the sum of AL and CL:
RL = AL + CL. The value for AL and CL are programmable via the MR and EMR
commands, respectively. Each subsequent data-out element will be valid nominally at
the next positive or negative clock edge (at the next crossing of CK and CK#). Figure 48
on page 85 shows examples of RL based on different AL and CL settings.
DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state
on DQS and the HIGH state on DQS# are known as the read preamble (tRPRE). The LOW
state on DQS and the HIGH state on DQS# coincident with the last data-out element are
known as the read postamble (tRPST).
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out
window hold), and the valid data window are depicted in Figure 57 on page 92 and
Figure 58 on page 93. A detailed explanation of tDQSCK (DQS transition skew to CK) and
tAC (data-out transition skew to CK) is shown in Figure 59 on page 94.
Data from any READ burst may be concatenated with data from a subsequent READ
command to provide a continuous flow of data. The first data element from the new
burst follows the last element of a completed burst. The new READ command should be
issued x cycles after the first READ command, where x equals BL/2 cycles (see Figure 49
on page 86).
Nonconsecutive read data is illustrated in Figure 50 on page 87. Full-speed random read
accesses within a page (or pages) can be performed. DDR2 SDRAM supports the use of
concurrent auto precharge timing (see Table 41 on page 90).
DDR2 SDRAM does not allow interrupting or truncating of any READ burst using BL = 4
operations. Once the BL = 4 READ command is registered, it must be allowed to
complete the entire READ burst. However, a READ (with auto precharge disabled) using
BL = 8 operation may be interrupted and truncated only by another READ burst as long
as the interruption occurs on a 4-bit boundary due to the 4n prefetch architecture of
DDR2 SDRAM. As shown in Figure 51 on page 87, READ burst BL = 8 operations may not
be interrupted or truncated with any other command except another READ command.
Data from any READ burst must be completed before a subsequent WRITE burst is
allowed. An example of a READ burst followed by a WRITE burst is shown in Figure 52 on
page 88. The tDQSS (NOM) case is shown (tDQSS [MIN] and tDQSS [MAX] are defined in
Figure 60 on page 96.)
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Operations
Figure 48:
READ Latency
T0
T1
T2
T3
READ
NOP
NOP
NOP
T3n
T4
T4n
T5
CK#
CK
Command
NOP
NOP
Bank a,
Col n
Address
RL = 3 (AL = 0, CL = 3)
DQS, DQS#
DO
n
DQ
T0
T1
T2
T3
T4
T4n
READ
NOP
NOP
NOP
NOP
T5
T5n
CK#
CK
Command
NOP
Bank a,
Col n
Address
AL = 1
CL = 3
RL = 4 (AL = 1 + CL = 3)
DQS, DQS#
DO
n
DQ
T0
T1
T2
T3
READ
NOP
NOP
NOP
T3n
T4
T4n
T5
CK#
CK
Command
NOP
NOP
Bank a,
Col n
Address
RL = 4 (AL = 0, CL = 4)
DQS, DQS#
DO
n
DQ
Transitioning Data
Notes:
1.
2.
3.
4.
Don’t Care
DO n = data-out from column n.
BL = 4.
Three subsequent elements of data-out appear in the programmed order following DO n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
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Operations
Figure 49:
Consecutive READ Bursts
T0
T1
T2
T3
Command
READ
NOP
READ
NOP
Address
Bank,
Col n
CK#
T3n
T4
T4n
T5n
T5
T6n
T6
CK
NOP
NOP
NOP
Bank,
Col b
tCCD
RL = 3
DQS, DQS#
DO
n
DQ
T0
T1
T2
Command
READ
NOP
READ
Address
Bank,
Col n
CK#
T2n
T3
DO
b
T3n
T4
T4n
T5
T5n
T6n
T6
CK
NOP
NOP
NOP
NOP
Bank,
Col b
tCCD
RL = 4
DQS, DQS#
DO
n
DQ
Transitioning Data
Notes:
1.
2.
3.
4.
5.
6.
DO
b
Don’t Care
DO n (or b) = data-out from column n (or column b).
BL = 4.
Three subsequent elements of data-out appear in the programmed order following DO n.
Three subsequent elements of data-out appear in the programmed order following DO b.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Example applies only when READ commands are issued to same device.
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Operations
Figure 50:
Nonconsecutive READ Bursts
CK#
CK
Command
T0
T1
T2
T3
T3n
READ
NOP
NOP
READ
Address
Bank,
Col n
T4
T4n
NOP
T5
T6
T6n
NOP
NOP
T7
T7n
T8
NOP
NOP
Bank,
Col b
CL = 3
DQS, DQS#
DO
n
DQ
DO
b
T4n
T0
T1
T2
T3
T4
Command
READ
NOP
NOP
READ
NOP
Address
Bank,
Col n
CK#
CK
T5
T5n
NOP
T6
T7
T7n
NOP
NOP
T8
NOP
Bank,
Col b
CL = 4
DQS, DQS#
DO
n
DQ
DO
b
Transitioning Data
Notes:
Figure 51:
1.
2.
3.
4.
5.
6.
Don’t Care
DO n (or b) = data-out from column n (or column b).
BL = 4.
Three subsequent elements of data-out appear in the programmed order following DO n.
Three subsequent elements of data-out appear in the programmed order following DO b.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Example applies when READ commands are issued to different devices or nonconsecutive
READs.
READ Interrupted by READ
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Command
READ1
NOP2
READ3
NOP2
Valid
Valid
Valid
Valid
Valid
Valid
Address
Valid4
CK#
CK
Valid4
Valid5
A10
DQS, DQS#
DO
DQ
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
CL = 3 (AL = 0)
tCCD
CL = 3 (AL = 0)
Transitioning Data
Notes:
Don’t Care
1. BL = 8 required; auto precharge must be disabled (A10 = LOW).
2. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be issued to
banks used for READs at T0 and T2.
3. Interrupting READ command must be issued exactly 2 × tCK from previous READ.
4. READ command can be issued to any valid bank and row address (READ command at T0 and
T2 can be either same bank or different bank).
5. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the interrupting READ command.
6. Example shown uses AL = 0; CL = 3, BL = 8, shown with nominal tAC, tDQSCK, and tDQSQ.
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Operations
Figure 52:
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
ACT n
READ n
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
READ-to-WRITE
DQS, DQS#
tRCD = 3
WL = RL - 1 = 4
DO
n
DQ
AL = 2
DO
n+1
DO
n+2
DO
n+3
DI
n
DI
n+1
DI
n+2
DI
n+3
CL = 3
RL = 5
Transitioning Data
Notes:
Don’t Care
1. BL = 4; CL = 3; AL = 2.
2. Shown with nominal tAC, tDQSCK, and tDQSQ.
READ with Precharge
A READ burst may be followed by a PRECHARGE command to the same bank, provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command
spacing to the same bank has two requirements that must be satisfied: AL + BL/2 clocks
and tRTP. tRTP is the minimum time from the rising clock edge that initiates the last 4-bit
prefetch of a READ command to the PRECHARGE command. For BL = 4, this is the time
from the actual READ (AL after the READ command) to PRECHARGE command. For
BL = 8, this is the time from AL + 2 × CK after the READ-to-PRECHARGE command.
Following the PRECHARGE command, a subsequent command to the same bank
cannot be issued until tRP is met. However, part of the row precharge time is hidden
during the access of the last data elements.
Examples of READ-to-PRECHARGE for BL = 4 are shown in Figure 53 and in Figure 54 on
page 89 for BL = 8. The delay from READ-to-PRECHARGE period to the same bank is
AL + BL/2 - 2CK + MAX (tRTP/tCK or 2 × CK) where MAX means the larger of the two.
Figure 53:
READ-to-PRECHARGE – BL = 4
CK#
CK
Command
T0
4-bit
prefetch
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
PRE
NOP
NOP
ACT
NOP
READ
AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK)
Address
Bank a
A10
AL = 1
DQS, DQS#
Bank a
Bank a
Valid
Valid
CL = 3
≥tRTP (MIN)
DQ
DO
≥tRAS (MIN)
DO
DO
DO
≥tRP (MIN)
≥tRC (MIN)
Transitioning Data
Notes:
1.
2.
3.
Don’t Care
RL = 4 (AL = 1, CL = 3); BL = 4.
≥ 2 clocks.
Shown with nominal tAC, tDQSCK, and tDQSQ.
tRTP
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Operations
Figure 54:
READ-to-PRECHARGE – BL = 8
CK#
CK
Command
T0
First 4-bit
prefetch
T1
READ
NOP
T2
Second 4-bit
prefetch
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
PRE
NOP
NOP
ACT
AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK)
Address
Bank a
A10
AL = 1
Bank a
Bank a
Valid
Valid
CL = 3
DQS, DQS#
DQ
DO
≥ tRTP (MIN)
DO
DO
DO
DO
DO
DO
DO
≥ tRP (MIN)
≥ tRAS (MIN)
≥ tRC (MIN)
Transitioning Data
Notes:
1.
2.
3.
Don’t Care
RL = 4 (AL = 1, CL = 3); BL = 8.
≥ 2 clocks.
Shown with nominal tAC, tDQSCK, and tDQSQ.
tRTP
READ with Auto Precharge
If A10 is HIGH when a READ command is issued, the READ with auto precharge function
is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising clock
edge that is AL + (BL/2) cycles later than the READ with auto precharge command
provided tRAS (MIN) and tRTP are satisfied. If tRAS (MIN) is not satisfied at this rising
clock edge, the start point of the auto precharge operation will be delayed until tRAS
(MIN) is satisfied. If tRTP (MIN) is not satisfied at this rising clock edge, the start point of
the auto precharge operation will be delayed until tRTP (MIN) is satisfied. When the
internal precharge is pushed out by tRTP, tRP starts at the point where the internal
precharge happens (not at the next rising clock edge after this event).
When BL = 4, the minimum time from READ with auto precharge to the next ACTIVATE
command is AL + (tRTP + tRP)/tCK. When BL = 8, the minimum time from READ with
auto precharge to the next ACTIVATE command is AL + 2 clocks + (tRTP + tRP)/tCK. The
term (tRTP + tRP)/tCK is always rounded up to the next integer. A general purpose equation can also be used: AL + BL/2 - 2CK + (tRTP + tRP)/tCK. In any event, the internal
precharge does not start earlier than two clocks after the last 4-bit prefetch.
READ with auto precharge command may be applied to one bank while another bank is
operational. This is referred to as concurrent auto precharge operation, as noted in
Table 41 on page 90. Examples of READ with precharge and READ with auto precharge
with applicable timing requirements are shown in Figure 55 on page 90 and Figure 56 on
page 91, respectively.
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Operations
Table 41:
READ Using Concurrent Auto Precharge
From
Command
(Bank n)
To Command
(Bank m)
Minimum Delay
(with Concurrent Auto Precharge)
READ with
auto
precharge
READ or READ with auto precharge
WRITE or WRITE with auto precharge
PRECHARGE or ACTIVATE
BL/2
(BL/2) + 2
1
Figure 55:
Units
t
CK
CK
t
CK
t
Bank Read – Without Auto Precharge
CK#
T0
T1
T2
T3
T4
NOP1
READ2
T5
T6
T7
T7n
NOP1
PRE3
NOP1
T8
T8n
T9
CK
tCK
tCH
tCL
CKE
Command
NOP1
ACT
NOP1
NOP1
ACT
tRTP4
Address
RA
Col n
RA
All banks
A10
RA
5
RA
One bank
Bank address
Bank x
Bank x6
Bank x
tRCD
Bank x
CL = 3
tRAS3
tRP
tRC
DM
tDQSCK (MIN)
Case 1: tAC (MIN) and tDQSCK (MIN)
7
tRPRE
tRPST
7
DQS, DQS#
tLZ (MIN)
DO
n
DQ8
tLZ (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
7
tRPRE
tAC (MIN)
tDQSCK (MAX)
tHZ (MIN)
tRPST
7
DQS, DQS#
tLZ (MAX)
DQ8
DO
n
tLZ (MIN)
tAC (MAX)
Transitioning Data
Notes:
tHZ (MAX)
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4 and AL = 0 in the case shown.
3. The PRECHARGE command can only be applied at T6 if tRAS (MIN) is met.
4. READ-to-PRECHARGE = AL + BL/2 -2CK + MAX (tRTP/tCK or 2CK).
5. Disable auto precharge.
6. “Don’t Care” if A10 is HIGH at T5.
7. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level, but
to when the device begins to drive or no longer drives, respectively.
8. DO n = data-out from column n; subsequent elements are applied in the programmed
order.
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Operations
Figure 56:
CK#
Bank Read – with Auto Precharge
T1
T0
T2
T3
T4
T5
T6
T7
T7n
READ2,3
NOP1
NOP1
NOP1
NOP1
T8
T8n
CK
tCK
tCH
tCL
CKE
Command1
NOP1
ACT
NOP1
ACT
Col n
RA
Address
NOP1
RA
4
A10
RA
RA
Bank address
Bank x
Bank x
Bank x
AL = 1
CL = 3
tRCD
tRTP
tRP
tRAS
tRC
DM
tDQSCK (MIN)
Case 1: tAC (MIN) and tDQSCK (MIN)
tRPRE
5
tRPST
5
DQS, DQS#
tLZ (MIN)
DO
n
DQ6
tLZ (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
5
tAC (MIN)
tDQSCK (MAX)
tRPRE
tHZ (MIN)
tRPST
5
DQS, DQS#
tLZ (MAX)
DQ6
DO
n
4-bit
prefetch
Internal
precharge
tLZ (MAX)
tAC (MAX)
Transitioning Data
Notes:
tHZ (MAX)
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4, RL = 4 (AL = 1, CL = 3) in the case shown.
3. The DDR2 SDRAM internally delays auto precharge until both tRAS (MIN) and tRTP (MIN)
have been satisfied.
4. Enable auto precharge.
5. I/O balls, when entering or exiting HIGH-Z, are not referenced to a specific voltage level,
but to when the device begins to drive or no longer drives, respectively.
6. DO n = data-out from column n; subsequent elements are applied in the programmed
order.
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512Mb: x4, x8, x16 DDR2 SDRAM
Operations
Figure 57:
x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window
T1
T2
T2n
T3
T3n
T4
CK#
CK
tHP1
tHP1
tHP1
tHP1
tDQSQ2
tDQSQ2
tHP1
tHP1
tDQSQ2
tDQSQ2
DQS, DQS#3
DQ (last data valid)
DQ4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ (first data no longer valid)
tQH5
tQH5
tQH5
tQH5
tQHS
tQHS
tQHS
tQHS
DQ (last data valid)
T2
T2n
T3
T3n
DQ (first data no longer valid)
T2
T2n
T3
T3n
All DQs and DQS collectively6
T2
T2n
Data
valid
window
Data
valid
window
T3
T3n
Earliest signal transition
Latest signal transition
Notes:
1.
2.
3.
4.
5.
6.
Data
valid
window
Data
valid
window
tHP
is the lesser of tCL or tCH clock transitions collectively when a bank is active.
is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transitions, and ends with the last valid transition of DQ.
DQ transitioning after the DQS transition defines the tDQSQ window. DQS transitions at T2
and at T2n are “early DQS,” at T3 are “nominal DQS,” and at T3n are “late DQS.”
DQ0, DQ1, DQ2, DQ3 for x4 or DQ0–DQ7 for x8.
tQH is derived from tHP: tQH = tHP - tQHS.
The data valid window is derived for each DQS transition and is defined as tQH - tDQSQ.
tDQSQ
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Operations
Figure 58:
x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window
CK#
T1
T2
T2n
T3
T3n
T4
CK
tHP1
tHP1
tHP1
tDQSQ2
tHP1
tHP1
tHP1
tDQSQ2
tDQSQ2
tDQSQ2
tQH5
tQHS
tQH5
tQHS
tQH5
tQHS
LDQS, LDSQ#3
Lower byte
DQ (last data valid)4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ (first data no longer valid)4
tQH5
tQHS
DQ (last data valid)4
T2
T2n
T3
T3n
DQ (first data no longer valid)4
T2
T2n
T3
T3n
DQ0–DQ7 and LDQS collectively6
T2
T2n
T3
T3n
Data valid
window
tDQSQ2
Data valid
window
tDQSQ2
Data valid
Data valid
window
window
tDQSQ2
tDQSQ2
UDQS, UDQS#3
Upper byte
DQ (last data valid)7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ (first data no longer valid)7
tQH5
tQH5
tQHS
tQH5
tQHS
tQH5
tQHS
tQHS
DQ (last data valid)7
T2
T2n
DQ (first data no longer valid)7
T2
T2n
DQ8–DQ15 and UDQS collectively6
T2
T2n
T3
T3n
Data valid
window
Data valid
window
Data valid
window
Data valid
window
Notes:
1.
2.
3.
4.
5.
6.
7.
T3
T3
T3n
T3n
tHP
is the lesser of tCL or tCH clock transitions collectively when a bank is active.
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transitions, and ends with the last valid transition of DQ.
DQ transitioning after the DQS transitions define the tDQSQ window. LDQS defines the
lower byte, and UDQS defines the upper byte.
DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
tQH is derived from tHP: tQH = tHP - tQHS.
The data valid window is derived for each DQS transition and is tQH - tDQSQ.
DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
t
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Operations
Figure 59:
Data Output Timing – tAC and tDQSCK
T01
T1
T2
T3
T3n
T4
T4n
T5
T5n
T6
T6n
T7
CK#
CK
tLZ (MIN)
tRPRE
tDQSCK2 (MIN) tDQSCK2 (MAX)
tHZ (MAX)
tRPST
DQS, DQS# or
LDQS, LDQS#/UDQ, UDQS#3
DQ (last data valid)
T3
DQ (first data valid)
T3
All DQs collectively4
Notes:
T3n
T3
tLZ (MIN)
T3n
T3n
T4
T4
T4n
T4n
T4
tAC5 (MIN)
T4n
T5
T5
T5
tAC5 (MAX)
T5n
T5n
T5n
T6
T6
T6
T6n
T6n
T6n
tHZ (MAX)
1. READ command with CL = 3, AL = 0 issued at T0.
2. tDQSCK is the DQS output window relative to CK and is the long-term component of DQS
skew.
3. DQ transitioning after DQS transitions define tDQSQ window.
4. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
5. tAC is the DQ output window relative to CK and is the “long term” component of DQ skew.
6. tLZ (MIN) and tAC (MIN) are the first valid signal transitions.
7. tHZ (MAX) and tAC (MAX) are the latest valid signal transitions.
8. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level, but
to when the device begins to drive or no longer drives, respectively.
WRITE
WRITE bursts are initiated with a WRITE command. DDR2 SDRAM uses WL equal to RL
minus one clock cycle (WL = RL - 1CK) (see "READ" on page 68). The starting column
and bank addresses are provided with the WRITE command, and auto precharge is
either enabled or disabled for that access. If auto precharge is enabled, the row being
accessed is precharged at the completion of the burst.
Note:
For the WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on
DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first rising DQS edge is WL ±tDQSS.
Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as
±tDQSS. tDQSS is specified with a relatively wide range (25 percent of one clock cycle).
All of the WRITE diagrams show the nominal case, and where the two extreme cases
(tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included.
Figure 60 on page 96 shows the nominal case and the extremes of tDQSS for BL = 4. Upon
completion of a burst, assuming no other commands have been initiated, the DQ will
remain High-Z and any additional input data will be ignored.
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Operations
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide continuous flow of input data. The first data element from the new burst is
applied after the last element of a completed burst. The new WRITE command should
be issued x cycles after the first WRITE command, where x equals BL/2.
Figure 61 on page 97 provides examples of concatenated bursts of BL = 4 and how fullspeed random write accesses within a page or pages can be performed. An example of
nonconsecutive WRITEs is shown in Figure 62 on page 97. DDR2 SDRAM supports
concurrent auto precharge options, as shown in Table 42 on page 95.
DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4
operation. Once the BL = 4 WRITE command is registered, it must be allowed to
complete the entire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto
precharge disabled) might be interrupted and truncated only by another WRITE burst as
long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architecture
of DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or truncated
with any command except another WRITE command, as shown in Figure 63 on page 98.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE, tWTR should be met, as shown in Figure 64 on page 99. The number of clock
cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is greater. Data for any
WRITE burst may be followed by a subsequent PRECHARGE command. tWR must be
met, as shown in Figure 65 on page 100. tWR starts at the end of the data burst, regardless of the data mask condition.
Table 42:
WRITE Using Concurrent Auto Precharge
From Command
(Bank n)
To Command
(Bank m)
Minimum Delay
(with Concurrent Auto Precharge)
WRITE with auto
precharge
READ or READ with auto precharge
WRITE or WRITE with auto
precharge
PRECHARGE or ACTIVATE
(CL - 1) + (BL/2) + tWTR
(BL/2)
tCK
1
tCK
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Units
tCK
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512Mb: x4, x8, x16 DDR2 SDRAM
Operations
Figure 60:
WRITE Burst
T0
T1
T2
Command
WRITE
NOP
NOP
Address
Bank a,
Col b
T2n
T3
T3n
T4
CK#
CK
tDQSS (NOM)
NOP
WL ± tDQSS
NOP
5
DQS, DQS#
DI
b
DQ
DM
tDQSS (MIN)
tDQSS5
WL - tDQSS
DQS, DQS#
DI
b
DQ
DM
tDQSS (MAX)
WL + tDQSS
tDQSS5
DQS, DQS#
DI
b
DQ
DM
Transitioning Data
Notes:
1.
2.
3.
4.
5.
Don’t Care
Subsequent rising DQS signals must align to the clock within tDQSS.
DI b = data-in for column b.
Three subsequent elements of data-in are applied in the programmed order following DI b.
Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
A10 is LOW with the WRITE command (auto precharge is disabled).
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Operations
Figure 61:
Consecutive WRITE-to-WRITE
CK#
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
CK
Command
WRITE
NOP
NOP
NOP
1
1
NOP
tCCD
WL = 2
WL = 2
Address
Bank,
Col b
tDQSS (NOM)
Bank,
Col n
WL ± tDQSS
1
DQS, DQS#
DI
b
DQ
DI
n
DM
Transitioning Data
Notes:
Figure 62:
1.
2.
3.
4.
5.
6.
Don’t Care
tDQSS.
Subsequent rising DQS signals must align to the clock within
DI b, etc. = data-in for column b, etc.
Three subsequent elements of data-in are applied in the programmed order following DI b.
Three subsequent elements of data-in are applied in the programmed order following DI n.
Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
Each WRITE command may be to any bank.
Nonconsecutive WRITE-to-WRITE
CK#
T0
T1
T2
NOP
NOP
T2n
T3
T3n
T4
T4n
T5
T5n
T6
T6n
CK
Command
WRITE
WRITE
Address
tDQSS (NOM)
NOP
NOP
NOP
1
1
WL = 2
WL = 2
Bank,
Col b
Bank,
Col n
WL ± tDQSS
1
DQS, DQS#
DI
b
DQ
DI
n
DM
Transitioning Data
Notes:
1.
2.
3.
4.
5.
6.
Don’t Care
tDQSS.
Subsequent rising DQS signals must align to the clock within
DI b (or n), etc. = data-in for column b (or column n).
Three subsequent elements of data-in are applied in the programmed order following DI b.
Three subsequent elements of data-in are applied in the programmed order following DI n.
Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
Each WRITE command may be to any bank.
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Operations
Figure 63:
CK#
CK
Command
Address
WRITE Interrupted by WRITE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
WRITE1 a
NOP2
WRITE3 b
NOP2
NOP2
NOP2
NOP2
Valid4
Valid4
Valid4
Valid5
Valid5
Valid6
A10
7
DQS, DQS#
DQ
WL = 3
2-clock requirement
DI
a
DI
a+1
7
DI
a+2
DI
a+3
DI
b
7
DI
b+1
DI
b+2
7
DI
b+3
DI
b+4
7
DI
b+5
DI
b+6
DI
b+7
WL = 3
Transitioning Data
Notes:
Don’t Care
1. BL = 8 required and auto precharge must be disabled (A10 = LOW).
2. The NOP or COMMAND INHIBIT commands are valid. The PRECHARGE command cannot be
issued to banks used for WRITEs at T0 and T2.
3. The interrupting WRITE command must be issued exactly 2 × tCK from previous WRITE.
4. The earliest WRITE-to-PRECHARGE timing for WRITE at T0 is WL + BL/2 + tWR where tWR
starts with T7 and not T5 (because BL = 8 from MR and not the truncated length).
5. The WRITE command can be issued to any valid bank and row address (WRITE command at
T0 and T2 can be either same bank or different bank).
6. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the interrupting WRITE command.
7. Subsequent rising DQS signals must align to the clock within tDQSS.
8. Example shown uses AL = 0; CL = 4, BL = 8.
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Operations
Figure 64:
CK#
WRITE-to-READ
T0
T1
T2
WRITE
NOP
NOP
T2n
T3
T3n
T4
T5
T6
T7
T8
NOP
READ
NOP
NOP
T9
T9n
CK
Command
NOP
NOP
NOP
tWTR1
Address
tDQSS (NOM)
Bank a,
Col b
Bank a,
Col n
WL ± tDQSS
CL = 3
2
DQS, DQS#
DI
b
DQ
DI
DM
tDQSS (MIN)
WL - tDQSS
CL = 3
2
DQS, DQS#
DI
b
DQ
DI
DM
tDQSS (MAX)
WL + tDQSS
CL = 3
2
DQS, DQS#
DI
b
DQ
DI
DM
Transitioning Data
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Don’t Care
tWTR
is required for any READ following a WRITE to the same device, but it is not required
between module ranks.
Subsequent rising DQS signals must align to the clock within tDQSS.
DI b = data-in for column b; DO n = data-out from column n.
BL = 4, AL = 0, CL = 3; thus, WL = 2.
One subsequent element of data-in is applied in the programmed order following DI b.
tWTR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
The number of clock cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is
greater.
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Operations
Figure 65:
WRITE-to-PRECHARGE
T0
T1
T2
WRITE
NOP
NOP
T2n
T3
T3n
T4
T5
NOP
NOP
T6
T7
NOP
PRE
CK#
CK
Command
NOP
tWR
Address
Bank a,
Col b
tRP
Bank,
(a or all)
tDQSS (NOM)
WL + tDQSS
1
DQS#, DQS
DI
b
DQ
DM
tDQSS (MIN)
WL - tDQSS
1
DQS#, DQS
DI
b
DQ
DM
tDQSS (MAX)
WL + tDQSS
1
DQS#, DQS
DI
b
DQ
DM
Transitioning Data
Notes:
Don’t Care
tDQSS.
1.
2.
3.
4.
5.
6.
Subsequent rising DQS signals must align to the clock within
DI b = data-in for column b.
Three subsequent elements of data-in are applied in the programmed order following DI b.
BL = 4, CL = 3, AL = 0; thus, WL = 2.
tWR is referenced from the first positive CK edge after the last data-in pair.
The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE
and WRITE commands may be to different banks, in which case tWR is not required and the
PRECHARGE command could be applied earlier.
7. A10 is LOW with the WRITE command (auto precharge is disabled).
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Operations
Figure 66:
CK#
Bank Write – Without Auto Precharge
T1
T0
CK
T3
T4
T5
WRITE2
NOP1
NOP1
T2
tCK
tCH
T5n
T6
T6n
T7
T8
T9
NOP1
NOP1
PRE
tCL
CKE
Command
NOP1
ACT
NOP1
Address
RA
Col n
A10
RA
3
NOP1
All banks
One bank
Bank address
Bank x
Bank x4
Bank x
tRCD
tWR
WL = 2
tRP
tRAS
WL ± tDQSS (NOM)
5
DQS, DQS#
tWPRE
tDQSL tDQSH tWPST
DI
n
DQ6
DM
Transitioning Data
Notes:
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4 and AL = 0 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T9.
5. Subsequent rising DQS signals must align to the clock within tDQSS.
6. DI n = data-in for column n; subsequent elements are applied in the programmed order.
7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.
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Operations
Figure 67:
CK#
Bank Write – with Auto Precharge
T1
T0
CK
T2
tCK
tCH
T3
T4
T5
WRITE2
NOP1
NOP1
T5n
T6
T6n
T7
T8
T9
NOP1
NOP1
NOP1
tCL
CKE
Command
NOP1
ACT
Address
RA
A10
RA
NOP1
NOP1
Col n
3
Bank address
Bank x
Bank x
tRCD
WR4
WL = 2
tRP
tRAS
WL ±tDQSS (NOM)
5
DQS, DQS#
tWPRE
tDQSL tDQSH tWPST
DI
n
DQ6
DM
Transitioning Data
Notes:
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4 and AL = 0 in the case shown.
3. Enable auto precharge.
4. WR is programmed via MR9–MR11 and is calculated by dividing tWR (in ns) by tCK and
rounding up to the next integer value.
5. Subsequent rising DQS signals must align to the clock within tDQSS.
6. DI n = data-in from column n; subsequent elements are applied in the programmed order.
7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.
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Operations
Figure 68:
CK#
CK
WRITE – DM Operation
T0
T1
T2
tCK
T3
tCH
T4
T5
T6
NOP1
NOP1
WL = 2
NOP1
T6n
T7
T7n
T8
T9
T10
T11
NOP1
NOP1
NOP1
PRE
tCL
CKE
Command
NOP1
ACT
NOP1
WRITE2
AL = 1
Address
RA
Col n
A10
RA
3
NOP1
All banks
One bank
Bank address
Bank x
Bank x4
Bank x
tRCD
tWR5
tRPA
tRAS
WL ±tDQSS (NOM)
6
DQS, DQS#
tDQSL tDQSH tWPST
tWPRE
DQ7
DI
n
DM
Transitioning Data
Notes:
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4, AL = 1, and WL = 2 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T11.
5. tWR starts at the end of the data burst regardless of the data mask condition.
6. Subsequent rising DQS signals must align to the clock within tDQSS.
7. DI n = data-in for column n; subsequent elements are applied in the programmed order.
8. tDSH is applicable during tDQSS (MIN) and is referenced from CK T6 or T7.
9. tDSS is applicable during tDQSS (MAX) and is referenced from CK T7 or T8.
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Operations
Figure 69:
Data Input Timing
T0
T1
T1n
T2
T2n
T3
T3n
T4
CK#
CK
tDSH1
tDSS2
tDSH1
tDSS2
tDQSH
tWPST
WL - tDQSS (NOM)
3
DQS, DQS#
tWPRE
DQ
tDQSL
DI
DM
Transitioning Data
Notes:
1.
2.
3.
4.
5.
6.
Don’t Care
tDSH
(MIN) generally occurs during tDQSS (MIN).
(MIN) generally occurs during tDQSS (MAX).
Subsequent rising DQS signals must align to the clock within tDQSS.
WRITE command issued at T0.
For x16, LDQS controls the lower byte and UDQS controls the upper byte.
WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0.
tDSS
PRECHARGE
PRECHARGE can be initiated by either a manual PRECHARGE command or by an auto
precharge in conjunction with either a READ or WRITE command. PRECHARGE will
deactivate the open row in a particular bank or the open row in all banks. The
PRECHARGE operation is shown in the previous READ and WRITE operation sections.
During a manual PRECHARGE command, the A10 input determines whether one or all
banks are to be precharged. In the case where only one bank is to be precharged, bank
address inputs determine the bank to be precharged. When all banks are to be
precharged, the bank address inputs are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and must be activated prior to
any READ or WRITE commands being issued to that bank. When a single-bank
PRECHARGE command is issued, tRP timing applies. When the PRECHARGE (ALL)
command is issued, tRPA timing applies, regardless of the number of banks opened.
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Operations
REFRESH
The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average
interval of 7.8125µs (MAX) and all rows in all banks must be refreshed at least once every
64ms. The refresh period begins when the REFRESH command is registered and ends
tRFC (MIN) later. The average interval must be reduced to 3.9µs (MAX) when T exceeds
C
+85°C.
Figure 70:
Refresh Mode
T0
T3
T4
Ta0
Ta1
Tb0
Tb1
Tb2
NOP1
REF
NOP1
REF2
NOP1
NOP1
ACT
T2
T1
CK#
CK
tCK
tCH
tCL
CKE
Command
NOP1
PRE
NOP1
Address
RA
All banks
A10
RA
One bank
Bank address
Bank(s)3
BA
DQS, DQS#4
DQ4
DM4
tRP
tRFC (MIN)
tRFC2
Indicates A Break in
Time Scale
Notes:
Don’t Care
1. NOP commands are shown for ease of illustration; other valid commands may be possible at
these times. CKE must be active during clock positive transitions.
2. The second REFRESH is not required and is only shown as an example of two back-to-back
REFRESH commands.
3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active
(must precharge all active banks).
4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
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Operations
SELF REFRESH
The SELF REFRESH command is initiated with CKE is LOW. The differential clock should
remain stable and meet tCKE specifications at least 1 × tCK after entering self refresh
mode. The procedure for exiting self refresh requires a sequence of commands. First, the
differential clock must be stable and meet tCK specifications at least 1 × tCK prior to CKE
going back to HIGH. Once CKE is HIGH (tCKE [MIN] has been satisfied with three clock
registrations), the DDR2 SDRAM must have NOP or DESELECT commands issued for
tXSNR. A simple algorithm for meeting both refresh and DLL requirements is to apply
NOP or DESELECT commands for 200 clock cycles before applying any other command.
Figure 71:
Self Refresh
T0
T1
T2
Ta0
Ta1
Tb0
Ta2
Tc0
Td0
CK#
CK1
tCH
tCK1
tCL
tCK1
tISXR2
tCKE3
tIH
CKE1
Command
NOP
NOP4
REF
NOP4
Valid5
Valid5
tIH
ODT6
tAOFD/tAOFPD6
Address
Valid
Valid7
DQS#, DQS
DQ
DM
tRP8
tCKE (MIN)9
tXSNR2, 5, 10
tXSRD2, 7
Enter self refresh
mode (synchronous)
Exit self refresh
mode (asynchronous)
Indicates A Break in
Time Scale
Notes:
Don’t Care
1. Clock must be stable and meeting tCK specifications at least 1 × tCK after entering self
refresh mode and at least 1 × tCK prior to exiting self refresh mode.
2. Self refresh exit is asynchronous; however, tXSNR and tXSRD timing starts at the first rising
clock edge where CKE HIGH satisfies tISXR.
3. CKE must stay HIGH until tXSRD is met; however, if self refresh is being reentered, CKE may
go back LOW after tXSNR is satisfied.
4. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0, which
allows any nonREAD command.
5. tXSNR is required before any nonREAD command can be applied.
6. ODT must be disabled and RTT off (tAOFD and tAOFPD have been satisfied) prior to entering
self refresh at state T1.
7. tXSRD (200 cycles of CK) is required before a READ command can be applied at state Td0.
8. Device must be in the all banks idle state prior to entering self refresh mode.
9. After self refresh has been entered, tCKE (MIN) must be satisfied prior to exiting self
refresh.
10. Upon exiting SELF REFRESH, ODT must remain LOW until tXSRD is satisfied.
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Operations
Power-Down Mode
DDR2 SDRAMs support multiple power-down modes that allow significant power
savings over normal operating modes. CKE is used to enter and exit different powerdown modes. Power-down entry and exit timings are shown in Figure 72 on page 108.
Detailed power-down entry conditions are shown in Figures 73–80. The CKE Truth Table,
Table 43, is shown on page 109.
DDR2 SDRAMs require CKE to be registered HIGH (active) at all times that an access is
in progress—from the issuing of a READ or WRITE command until completion of the
burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined
when the read postamble is satisfied; for WRITEs, a burst completion is defined when
the write postamble and tWR (WRITE-to-PRECHARGE command) or tWTR (WRITE-toREAD command) are satisfied, as shown in Figures 75 and 76 on page 111. The number
of clock cycles required to meet tWTR is either two or tWTR/tCK, whichever is greater.
Power-down mode (see Figure 72 on page 108) is entered when CKE is registered LOW
coincident with a NOP or DESELECT command. CKE is not allowed to go LOW during a
mode register or extended mode register command time, or while a READ or WRITE
operation is in progress. If power-down occurs when all banks are idle, this mode is
referred to as precharge power-down. If power-down occurs when there is a row active in
any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK#, ODT, and CKE. For maximum
power savings, the DLL is frozen during precharge power-down. Exiting active powerdown requires the device to be at the same voltage and frequency as when it entered
power-down. Exiting precharge power-down requires the device to be at the same
voltage as when it entered power-down; however, the clock frequency is allowed to
change (see "Precharge Power-Down Clock Frequency Change" on page 113).
The maximum duration for either active or precharge power-down is limited by the
refresh requirements of the device tRFC (MAX). The minimum duration for power-down
entry and exit is limited by the tCKE (MIN) parameter. The following must be maintained while in power-down mode: CKE LOW, a stable clock signal, and stable power
supply signals at the inputs of the DDR2 SDRAM. All other input signals are “Don’t Care”
except ODT. Detailed ODT timing diagrams for different power-down modes are shown
in Figure 83 on page 118–Figure 90 on page 122.
The power-down state is synchronously exited when CKE is registered HIGH (in
conjunction with a NOP or DESELECT command), as shown in Figure 72 on page 108.
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Operations
Figure 72:
Power-Down
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
Valid
Valid
CK#
CK
Command
tCH
tCK
Valid1
tCL
NOP
tCKE (MIN)2
tIH
CKE
tIH
tIS
Address
tCKE (MIN)2
Valid
Valid
Valid
tXP3, tXARD4
tXARDS5
DQS, DQS#
DQ
DM
Enter
power-down
mode6
Notes:
Exit
power-down
mode
Don’t Care
1. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVATE (or if
at least one row is already active), then the power-down mode shown is active powerdown.
2. tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive clock
edges. CKE must remain at the valid input level the entire time it takes to achieve the three
clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid
level during the time period of tIS + 2 × tCK + tIH. CKE must not transition during its tIS and
t
IH window.
3. tXP timing is used for exit precharge power-down and active power-down to any nonREAD
command.
4. tXARD timing is used for exit active power-down to READ command if fast exit is selected
via MR (bit 12 = 0).
5. tXARDS timing is used for exit active power-down to READ command if slow exit is selected
via MR (bit 12 = 1).
6. No column accesses are allowed to be in progress at the time power-down is entered. If the
DLL was not in a locked state when CKE went LOW, the DLL must be reset after exiting
power-down mode for proper READ operation.
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Operations
Table 43:
Truth Table – CKE
Notes 1–4 apply to the entire table
CKE
Current State
Previous
Cycle
(n - 1)
Current
Cycle (n)
L
L
L
L
H
H
H
H
L
H
L
H
L
L
L
H
Power-down
Self refresh
Bank(s) active
All banks idle
Notes:
Command (n) CS#,
RAS#, CAS#, WE#
Action (n)
X
Maintain power-down
DESELECT or NOP
Power-down exit
X
Maintain self refresh
DESELECT or NOP
Self refresh exit
DESELECT or NOP
Active power-down entry
DESELECT or NOP
Precharge power-down entry
REFRESH
Self refresh entry
Shown in Table 36 on page 63
Notes
5, 6
7, 8
6
7, 9, 10
7, 8, 11, 12
7, 8, 11
10, 12, 13
14
1. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n.
3. Command (n) is the command registered at clock edge n, and action (n) is a result of command (n).
4. The state of ODT does not affect the states described in this table. The ODT function is not
available during self refresh (see "ODT Timing" on page 117 for more details and specific
restrictions).
5. Power-down modes do not perform any REFRESH operations. The duration of power-down
mode is therefore limited by the refresh requirements.
6. “X” means “Don’t Care” (including floating around VREF) in self refresh and power-down.
However, ODT must be driven HIGH or LOW in power-down if the ODT function is enabled
via EMR.
7. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
8. Valid commands for power-down entry and exit are NOP and DESELECT only.
9. On self refresh exit, DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. READ commands may be issued only after tXSRD (200 clocks)
is satisfied.
10. Valid commands for self refresh exit are NOP and DESELECT only.
11. Power-down and self refresh can not be entered while READ or WRITE operations, LOAD
MODE operations, or PRECHARGE operations are in progress. See “SELF REFRESH” on
page 106 and “SELF REFRESH” on page 69 for a list of detailed restrictions.
12. Minimum CKE HIGH time is tCKE = 3 × tCK. Minimum CKE LOW time is tCKE = 3 × tCK. This
requires a minimum of 3 clock cycles of registration.
13. Self refresh mode can only be entered from the all banks idle state.
14. Must be a legal command, as defined in Table 36 on page 63.
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Operations
Figure 73:
CK#
READ-to-Power-Down or Self Refresh Entry
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
Valid
Valid
NOP1
T7
CK
Command
tCKE (MIN)
CKE
Address
Valid
A10
DQS, DQS#
DQ
DO
DO
RL = 3
DO
DO
Power-down2 or
self refresh entry
Transitioning Data
Notes:
Figure 74:
CK#
Don’t Care
1. In the example shown, READ burst completes at T5; earliest power-down or self refresh
entry is at T6.
2. Power-down or self refresh entry may occur after the READ burst completes.
READ with Auto Precharge-to-Power-Down or Self Refresh Entry
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
Valid
Valid
NOP1
T7
CK
Command
tCKE (MIN)
CKE
Address
Valid
A10
DQS, DQS#
DQ
RL = 3
DO
DO
DO
DO
Power-down or
self refresh2 entry
Transitioning Data
Notes:
Don’t Care
1. In the example shown, READ burst completes at T5; earliest power-down or self refresh
entry is at T6.
2. Power-down or self refresh entry may occur after the READ burst completes.
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Operations
Figure 75:
CK#
CK
Command
WRITE-to-Power-Down or Self-Refresh Entry
T0
T1
T2
T3
T4
T5
T6
T7
WRITE
NOP
NOP
NOP
Valid
Valid
Valid
NOP1
T8
tCKE (MIN)
CKE
Address
Valid
A10
DQS, DQS#
DQ
DO
DO
DO
DO
tWTR
WL = 3
Power-down or
self refresh entry1
Transitioning Data
Notes:
Figure 76:
CK#
CK
Command
Don’t Care
1. Power-down or self refresh entry may occur after the WRITE burst completes.
WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry
T0
T1
T2
T3
T4
T5
Ta0
Ta1
WRITE
NOP
NOP
NOP
Valid
Valid
Valid1
NOP
Ta2
tCKE (MIN)
CKE
Address
Valid
A10
DQS, DQS#
DQ
DO
DO
DO
DO
WR2
WL = 3
Power-down or
self refresh entry
Indicates A Break in
Time Scale
Notes:
Transitioning Data
Don’t Care
1. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may occur
1 x tCK later at Ta1, prior to tRP being satisfied.
2. WR is programmed through MR9–MR11 and represents (tWR [MIN]ns/tCK) rounded up to
next integer tCK.
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Operations
Figure 77:
REFRESH Command-to-Power-Down Entry
T0
T1
T2
Valid
REFRESH
NOP
T3
CK#
CK
Command
tCKE (MIN)
CKE
1 x tCK
Power-down1
entry
Don’t Care
Notes:
Figure 78:
1. The earliest precharge power-down entry may occur is at T2, which is 1 × tCK after the
REFRESH command. Precharge power-down entry occurs prior to tRFC (MIN) being satisfied.
ACTIVATE Command-to-Power-Down Entry
T0
T1
T2
Valid
ACT
NOP
T3
CK#
CK
Command
Address
Valid
tCKE (MIN)
CKE
1 tCK
Power-down1
entry
Don’t Care
Notes:
1. The earliest active power-down entry may occur is at T2, which is 1 × tCK after the ACTIVATE
command. Active power-down entry occurs prior to tRCD (MIN) being satisfied.
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Operations
Figure 79:
PRECHARGE Command-to-Power-Down Entry
CK#
T0
T1
T2
Valid
PRE
NOP
T3
CK
Command
Address
Valid
All banks
vs.
Single bank
A10
tCKE
(MIN)
CKE
1 x tCK
Power-down1
entry
Don’t Care
Notes:
Figure 80:
1. The earliest precharge power-down entry may occur is at T2, which is 1 × tCK after the PRECHARGE command. Precharge power-down entry occurs prior to tRP (MIN) being satisfied.
LOAD MODE Command-to-Power-Down Entry
CK#
T0
T1
T2
T3
Valid
LM
NOP
NOP
T4
CK
Command
Valid1
Address
tCKE (MIN)
CKE
tRP2
tMRD
Power-down3
entry
Don’t Care
Notes:
1. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.
2. All banks must be in the precharged state and tRP met prior to issuing LM command.
3. The earliest precharge power-down entry is at T3, which is after tMRD is satisfied.
Precharge Power-Down Clock Frequency Change
When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off
and CKE must be at a logic LOW level. A minimum of two differential clock cycles must
pass after CKE goes LOW before clock frequency may change. The device input clock
frequency is allowed to change only within minimum and maximum operating frequencies specified for the particular speed grade. During input clock frequency change, ODT
and CKE must be held at stable LOW levels. When the input clock frequency is changed,
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Operations
new stable clocks must be provided to the device before precharge power-down may be
exited, and DLL must be reset via MR after precharge power-down exit. Depending on
the new clock frequency, additional LM commands might be required to adjust the CL,
WR, AL, and so forth. settings to account for the frequency change. Depending on the
new clock frequency, an additional LM command might be required to appropriately set
the WR MR9, MR10, MR11. During the DLL relock period of 200 cycles, ODT must
remain off. After the DLL lock time, the DRAM is ready to operate with a new clock
frequency.
Figure 81:
Input Clock Frequency Change During Precharge Power-Down Mode
Previous clock frequency
T0
T1
T2
New clock frequency
T3
Ta1
Ta0
Ta2
Ta3
Ta4
Tb0
NOP
Valid
CK#
CK
tCH
tCL
tCH
tCK
tCL
tCK
2 x tCK (MIN)1
1 x tCK (MIN)2
tCKE (MIN)3
tCKE (MIN)3
CKE
Command
Address
Valid4
NOP
NOP
NOP
Valid
LM
DLL RESET
Valid
tXP
ODT
DQS, DQS#
DQ
High-Z
High-Z
DM
Enter precharge
power-down mode
Frequency
change
Exit precharge
power-down mode
200 x tCK
Indicates A Break in
Time Scale
Notes:
Don’t Care
1. A minimum of 2 × tCK is required after entering precharge power-down prior to changing
clock frequencies.
2. When the new clock frequency has changed and is stable, a minimum of 1 × tCK is required
prior to exiting precharge power-down.
3. Minimum CKE HIGH time is tCKE = 3 × tCK. Minimum CKE LOW time is tCKE = 3 × tCK. This
requires a minimum of three clock cycles of registration.
4. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down, which is required prior to the clock
frequency change.
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Operations
RESET
CKE LOW Anytime
DDR2 SDRAM applications may go into a reset state anytime during normal operation.
If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM
device resumes normal operation after reinitializing. All data will be lost during a reset
condition; however, the DDR2 SDRAM device will continue to operate properly if the
following conditions outlined in this section are satisfied.
The reset condition defined here assumes all supply voltages (VDD, VDDQ, VDDL, and
VREF ) are stable and meet all DC specifications prior to, during, and after the RESET
operation. All other input balls of the DDR2 SDRAM device are a “Don’t Care” during
RESET with the exception of CKE.
If CKE asynchronously drops LOW during any valid operation (including a READ or
WRITE burst), the memory controller must satisfy the timing parameter tDELAY before
turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM before
CKE is raised HIGH, at which time the normal initialization sequence must occur (see
"Initialization" on page 70). The DDR2 SDRAM device is now ready for normal operation
after the initialization sequence. Figure 82 on page 116 shows the proper sequence for a
RESET operation.
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Operations
Figure 82:
RESET Function
T0
T1
T2
T3
T4
T5
Ta0
tCK
Tb0
CK#
CK
tDELAY
tCL
tCL
tCKE (MIN)
1
CKE
ODT
Command
NOP2
READ
READ
NOP2
NOP2
NOP2
PRE
DM3
Address
Col n
Col n
All banks
A10
Bank address
DQS3
DQ3
Bank a
Bank b
High-Z
High-Z
High-Z
DO
DO
4
High-Z
DO
High-Z
RTT
T = 400ns (MIN)
tRPA
System
RESET
Start of normal5
initialization
sequence
Indicates A Break in
Time Scale
Notes:
Unknown
RTT On
Transitioning Data
Don’t Care
1. VDD, VDDL, VDDQ, VTT, and VREF must be valid at all times.
2. Either NOP or DESELECT command may be applied.
3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the appropriate configuration (x4, x8, x16).
4. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the completion of the burst.
5. Initialization timing is shown in Figure 38 on page 71.
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Operations
ODT Timing
Once a 12ns delay (tMOD) has been satisfied, and after the ODT function has been
enabled via the EMR LOAD MODE command, ODT can be accessed under two timing
categories. ODT will operate either in synchronous mode or asynchronous mode,
depending on the state of CKE. ODT can switch anytime except during self refresh mode
and a few clocks after being enabled via EMR, as shown in Figure 83 on page 118.
There are two timing categories for ODT—turn-on and turn-off. During active mode
(CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW,
MR[12 = 0]), tAOND, tAON, tAOFD, and tAOF timing parameters are applied, as shown in
Figure 85 on page 119.
During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1)
and precharge power-down mode (all banks/rows precharged and idle, CKE LOW),
tAONPD and tAOFPD timing parameters are applied, as shown in Figure 86 on page 119.
ODT turn-off timing, prior to entering any power-down mode, is determined by the
parameter tANPD (MIN), as shown in Figure 87 on page 120. At state T2, the ODT HIGH
signal satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD
(MIN) is satisfied, tAOFD and tAOF timing parameters apply. Figure 87 on page 120 also
shows the example where tANPD (MIN) is not satisfied because ODT HIGH does not
occur until state T3. When tANPD (MIN) is not satisfied, tAOFPD timing parameters
apply.
ODT turn-on timing prior to entering any power-down mode is determined by the
parameter tANPD, as shown in Figure 88 on page 120. At state T2, the ODT HIGH signal
satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD (MIN) is
satisfied, tAOND and tAON timing parameters apply. Figure 88 also shows the example
where tANPD (MIN) is not satisfied because ODT HIGH does not occur until state T3.
When tANPD (MIN) is not satisfied, tAONPD timing parameters apply.
ODT turn-off timing after exiting any power-down mode is determined by the parameter
tAXPD (MIN), as shown in Figure 89 on page 121. At state Ta1, the ODT LOW signal satis-
fies tAXPD (MIN) after exiting power-down mode at state T1. When tAXPD (MIN) is satisfied, tAOFD and tAOF timing parameters apply. Figure 89 also shows the example where
t
AXPD (MIN) is not satisfied because ODT LOW occurs at state Ta0. When tAXPD (MIN)
is not satisfied, tAOFPD timing parameters apply.
ODT turn-on timing after exiting either slow-exit power-down mode or precharge
power-down mode is determined by the parameter tAXPD (MIN), as shown in Figure 90
on page 122. At state Ta1, the ODT HIGH signal satisfies tAXPD (MIN) after exiting
power-down mode at state T1. When tAXPD (MIN) is satisfied, tAOND and tAON timing
parameters apply. Figure 90 also shows the example where tAXPD (MIN) is not satisfied
because ODT HIGH occurs at state Ta0. When tAXPD (MIN) is not satisfied, tAONPD
timing parameters apply.
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117
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Operations
Figure 83:
ODT Timing for Entering and Exiting Power-Down Mode
Synchronous
Synchronous or
Synchronous
Asynchronous
tANPD (3 tCKs)
First CKE latched LOW
tAXPD (8 tCKs)
First CKE latched HIGH
CKE
Any mode except
self refresh mode
Any mode except
self refresh mode
Active power-down fast (synchronous)
Active power-down slow (asynchronous)
Precharge power-down (asynchronous)
Applicable modes
tAOND/tAOFD
tAOND/tAOFD
tAOND/tAOFD
(synchronous)
tAONPD/tAOFPD
(asynchronous)
Applicable timing parameters
MRS Command to ODT Update Delay
During normal operation, the value of the effective termination resistance can be
changed with an EMRS set command. tMOD (MAX) updates the RTT setting.
Figure 84:
Timing for MRS Command to ODT Update Delay
T0
Command
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
EMRS1
NOP
NOP
NOP
NOP
NOP
CK#
CK
2
ODT2
tAOFD
tMOD
tIS
0ns
Internal
RTT setting
Old setting
Undefined
New setting
Indicates A Break in
Time Scale
Notes:
1. The LM command is directed to the mode register, which updates the information in EMR
(A6, A2), that is, RTT (nominal).
2. To prevent any impedance glitch on the channel, the following conditions must be met:
tAOFD must be met before issuing the LM command; ODT must remain LOW for the entire
duration of the tMOD window until tMOD is met.
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Operations
Figure 85:
ODT Timing for Active or Fast-Exit Power-Down Mode
T0
CK#
T1
CK
tCK
tCH
T2
T3
T4
T5
T6
tCL
Command
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Address
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CKE
tAOND
ODT
tAOFD
RTT
tAOF (MAX)
tAON (MIN)
tAON (MAX)
tAOF (MIN)
RTT Unknown
Figure 86:
RTT On
Don’t Care
ODT Timing for Slow-Exit or Precharge Power-Down Modes
T0
CK#
CK
T1
tCK
tCH
T2
T3
T4
T5
T6
T7
tCL
Command
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Address
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CKE
ODT
tAONPD (MAX)
tAONPD (MIN)
RTT
tAOFPD (MIN)
tAOFPD (MAX)
Transitioning RTT
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RTT Unknown
RTT On
Don’t Care
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Operations
Figure 87:
ODT Turn-Off Timings When Entering Power-Down Mode
CK#
T0
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
tANPD (MIN)
CKE
tAOFD
ODT
tAOF (MAX)
RTT
tAOF (MIN)
tAOFPD (MAX)
ODT
RTT
tAOFPD (MIN)
RTT Unknown
Figure 88:
RTT On
Don’t Care
ODT Turn-On Timing When Entering Power-Down Mode
CK#
T0
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
tANPD (MIN)
CKE
ODT
tAOND
tAON (MAX)
RTT
tAON (MIN)
ODT
tAONPD (MAX)
RTT
tAONPD (MIN)
Transitioning RTT
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RTT Unknown
RTT On
Don’t Care
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Operations
Figure 89:
CK#
ODT Turn-Off Timing When Exiting Power-Down Mode
T0
T1
T2
T3
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
tAXPD (MIN)
CKE
tCKE (MIN)
tAOFD
ODT
tAOF (MAX)
RTT
tAOF (MIN)
tAOFPD (MAX)
ODT
RTT
tAOFPD (MIN)
Indicates A Break In
Time Scale
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DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Transitioning RTT
121
RTT Unknown
RTT On
Don’t Care
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Operations
Figure 90:
CK#
ODT Turn-On Timing When Exiting Power-Down Mode
T0
T1
T2
T3
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
tAXPD (MIN)
CKE
tCKE (MIN)
ODT
tAOND
tAON (MAX)
RTT
tAON (MIN)
ODT
tAONPD (MAX)
RTT
tAONPD (MIN)
Indicates a break in
time scale
RTT Unknown
RTT On
TRANSITIONING RTT
Don’t Care
®
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Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although
considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
122
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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